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Volumn 32, Issue 2, 2005, Pages 139-162

Energy-efficient computations on FPGAs

Author keywords

Algorithm design; Embedded signal processing; Energy efficiency; FPGA; Performance optimization

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; ENERGY EFFICIENCY; OPTIMIZATION; PARAMETER ESTIMATION; PERFORMANCE; SIGNAL PROCESSING;

EID: 17044362170     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11227-005-0289-9     Document Type: Article
Times cited : (13)

References (21)
  • 2
    • 0028098424 scopus 로고
    • A linear systolic array for LU decomposition
    • E. Casseau, D. Degrugillier. A linear systolic array for LU decomposition. VLSI Design, 1994.
    • (1994) VLSI Design
    • Casseau, E.1    Degrugillier, D.2
  • 13
    • 12744275241 scopus 로고    scopus 로고
    • Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs
    • June
    • J. Ou, S. Choi, and V. K. Prasanna. Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs. International Journal of Embedded Systems, June 2004.
    • (2004) International Journal of Embedded Systems
    • Ou, J.1    Choi, S.2    Prasanna, V.K.3
  • 14
    • 18644386554 scopus 로고    scopus 로고
    • PyGen: A MATLAB/Simulink based tool for synthesizing parameterized and energy efficient designs using FPGAs
    • J. Ou and V. K. Prasanna. PyGen: A MATLAB/Simulink based tool for synthesizing parameterized and energy efficient designs using FPGAs. FCCM, 2004.
    • (2004) FCCM
    • Ou, J.1    Prasanna, V.K.2
  • 15
    • 0026170809 scopus 로고
    • On synthesizing optimal family of linear systolic arrays for matrix multiplication
    • V. K. Prasanna Kumar and Y. Tsai. On synthesizing optimal family of linear systolic arrays for matrix multiplication. IEEE Transactions on Computers, 40(6), 1991.
    • (1991) IEEE Transactions on Computers , vol.40 , Issue.6
    • Kumar, V.K.P.1    Tsai, Y.2
  • 19
    • 17044381917 scopus 로고    scopus 로고
    • Xilinx, www.xilinx.com.
  • 21
    • 12744250750 scopus 로고    scopus 로고
    • Scalable and modular algorithms for floating-point matrix multiplication on FPGAs
    • Dept. of Eletrical Engineering, University of Southern California
    • L. Zhuo and V. K. Prasanna. Scalable and modular algorithms for floating-point matrix multiplication on FPGAs. Technical report, Dept. of Eletrical Engineering, University of Southern California, 2004.
    • (2004) Technical Report
    • Zhuo, L.1    Prasanna, V.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.