-
2
-
-
62949182106
-
-
BPTM
-
BPTM, http://www.device.eecs.berkeley.edu/ptm/download.html/, 2008.
-
(2008)
-
-
-
4
-
-
0035308547
-
-
A.J.Bhavnagarwala, X. Tang, and M. J.D. The impact of intrinsic device fluctuations on cmos sram cell stability. IEEE Journal of Solid-State Circuits, 36:658-665, Apr 2001.
-
A.J.Bhavnagarwala, X. Tang, and M. J.D. The impact of intrinsic device fluctuations on cmos sram cell stability. IEEE Journal of Solid-State Circuits, 36:658-665, Apr 2001.
-
-
-
-
5
-
-
0142118150
-
Design and optimization of multithreshold cmos (mtcmos) circuits
-
Oct
-
M. Anis, S. Areibi, and M. Elmasry. Design and optimization of multithreshold cmos (mtcmos) circuits. IEEE Trans. CAD of Integrated Circuits and Systems, 22(10):1324-1342, Oct. 2003.
-
(2003)
IEEE Trans. CAD of Integrated Circuits and Systems
, vol.22
, Issue.10
, pp. 1324-1342
-
-
Anis, M.1
Areibi, S.2
Elmasry, M.3
-
6
-
-
33750815896
-
Read stability and write-ability analysis of sram cells for nanometer technologies
-
Nov
-
E. Grossar, M. Stucchi, K. Maex, and W. Dehaene. Read stability and write-ability analysis of sram cells for nanometer technologies. IEEE Journal of Solid-State Circuits, 41(11):2577-2588, Nov 2006.
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.11
, pp. 2577-2588
-
-
Grossar, E.1
Stucchi, M.2
Maex, K.3
Dehaene, W.4
-
9
-
-
1642310480
-
Circuit and microarchitectural techniques for reducing cache leakage power
-
N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge. Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. Very Large Scale Integr. Syst., 12(2):167-184, 2004.
-
(2004)
IEEE Trans. Very Large Scale Integr. Syst
, vol.12
, Issue.2
, pp. 167-184
-
-
Kim, N.S.1
Flautner, K.2
Blaauw, D.3
Mudge, T.4
-
10
-
-
0029288557
-
Trends in low-power ram circuit technologies
-
April
-
I. Kiyoo, S. Katsuro, and N. Yoshinobu. Trends in low-power ram circuit technologies. In Proc. of the IEEE, vol. 83, pp. 524-543, April 1995.
-
(1995)
Proc. of the IEEE
, vol.83
, pp. 524-543
-
-
Kiyoo, I.1
Katsuro, S.2
Yoshinobu, N.3
-
11
-
-
41549118603
-
Characterization of a novel nine-transistor sram cell
-
April
-
Z. Liu and V. Kursun. Characterization of a novel nine-transistor sram cell. IEEE Trans. VLSI Systems, 16(4):488-492, April 2008.
-
(2008)
IEEE Trans. VLSI Systems
, vol.16
, Issue.4
, pp. 488-492
-
-
Liu, Z.1
Kursun, V.2
-
12
-
-
4544332286
-
Modeling and estimation of failure probability due to parameter variations in nanoscale srams for yield enhancement
-
S. Mukhopadhyay, H. Mahmoodi, and K. Roy. Modeling and estimation of failure probability due to parameter variations in nanoscale srams for yield enhancement. In Proc. VLSI Circuits Symposium, pp. 64-67, 2004.
-
(2004)
Proc. VLSI Circuits Symposium
, pp. 64-67
-
-
Mukhopadhyay, S.1
Mahmoodi, H.2
Roy, K.3
-
14
-
-
2442716234
-
A 180 mv fft processor using subthreshold circuit techniques
-
A. Wang and A. Chandrakasan. A 180 mv fft processor using subthreshold circuit techniques. In Proc.IEEE ISSCC Dig. Tech. Papers, pages 229-293, 2004.
-
(2004)
Proc.IEEE ISSCC Dig. Tech. Papers
, pp. 229-293
-
-
Wang, A.1
Chandrakasan, A.2
|