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Volumn , Issue , 2009, Pages 307-312

Single ended static random access memory for low-Vdd, high-speed embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT DESIGN; VLSI CIRCUITS;

EID: 62949143893     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.38     Document Type: Conference Paper
Times cited : (3)

References (14)
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    • BPTM
    • BPTM, http://www.device.eecs.berkeley.edu/ptm/download.html/, 2008.
    • (2008)
  • 4
    • 0035308547 scopus 로고    scopus 로고
    • A.J.Bhavnagarwala, X. Tang, and M. J.D. The impact of intrinsic device fluctuations on cmos sram cell stability. IEEE Journal of Solid-State Circuits, 36:658-665, Apr 2001.
    • A.J.Bhavnagarwala, X. Tang, and M. J.D. The impact of intrinsic device fluctuations on cmos sram cell stability. IEEE Journal of Solid-State Circuits, 36:658-665, Apr 2001.
  • 6
    • 33750815896 scopus 로고    scopus 로고
    • Read stability and write-ability analysis of sram cells for nanometer technologies
    • Nov
    • E. Grossar, M. Stucchi, K. Maex, and W. Dehaene. Read stability and write-ability analysis of sram cells for nanometer technologies. IEEE Journal of Solid-State Circuits, 41(11):2577-2588, Nov 2006.
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.11 , pp. 2577-2588
    • Grossar, E.1    Stucchi, M.2    Maex, K.3    Dehaene, W.4
  • 10
    • 0029288557 scopus 로고
    • Trends in low-power ram circuit technologies
    • April
    • I. Kiyoo, S. Katsuro, and N. Yoshinobu. Trends in low-power ram circuit technologies. In Proc. of the IEEE, vol. 83, pp. 524-543, April 1995.
    • (1995) Proc. of the IEEE , vol.83 , pp. 524-543
    • Kiyoo, I.1    Katsuro, S.2    Yoshinobu, N.3
  • 11
    • 41549118603 scopus 로고    scopus 로고
    • Characterization of a novel nine-transistor sram cell
    • April
    • Z. Liu and V. Kursun. Characterization of a novel nine-transistor sram cell. IEEE Trans. VLSI Systems, 16(4):488-492, April 2008.
    • (2008) IEEE Trans. VLSI Systems , vol.16 , Issue.4 , pp. 488-492
    • Liu, Z.1    Kursun, V.2
  • 12
    • 4544332286 scopus 로고    scopus 로고
    • Modeling and estimation of failure probability due to parameter variations in nanoscale srams for yield enhancement
    • S. Mukhopadhyay, H. Mahmoodi, and K. Roy. Modeling and estimation of failure probability due to parameter variations in nanoscale srams for yield enhancement. In Proc. VLSI Circuits Symposium, pp. 64-67, 2004.
    • (2004) Proc. VLSI Circuits Symposium , pp. 64-67
    • Mukhopadhyay, S.1    Mahmoodi, H.2    Roy, K.3
  • 14
    • 2442716234 scopus 로고    scopus 로고
    • A 180 mv fft processor using subthreshold circuit techniques
    • A. Wang and A. Chandrakasan. A 180 mv fft processor using subthreshold circuit techniques. In Proc.IEEE ISSCC Dig. Tech. Papers, pages 229-293, 2004.
    • (2004) Proc.IEEE ISSCC Dig. Tech. Papers , pp. 229-293
    • Wang, A.1    Chandrakasan, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.