Optimal multi-processor SoC thermal simulation via adaptive differential equation solvers

Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

Volumn , Issue , 2009, Pages 139-146

  Zanini, Francesco ^a   Atienza, David ^a   Coskun, Ayse K ^b   Micheli, Giovanni De ^a  

^a EPFL   (Switzerland)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPROCESSING SYSTEMS; ORDINARY DIFFERENTIAL EQUATIONS; THERMOANALYSIS; VLSI CIRCUITS;

CRITICAL CHALLENGES; DIFFERENTIAL EQUATION SOLVERS; MULTI PROCESSOR SYSTEM ON CHIPS; MULTI-PROCESSOR SOC; ORDINARY DIFFERENTIAL EQUATION (ODE) SOLVERS; THERMAL BEHAVIORS; THERMAL SIMULATIONS; THERMAL SIMULATORS;

SYSTEM-ON-CHIP;

EID: 80555154205     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2009.6041344     Document Type: Conference Paper

References (20)

1. J. Li et al., Power-performance implications of thread-level parallelism in chip multiprocessors, Proc. ISPASS, 2005.
2. J. Deeney, Thermal modeling and measurement of large high power silicon devices with asymmetric power distribution, Proc. ISM, 2002.
3. B. Goplen et al., Efficient thermal placement of standard cells in 3D ICs using a force directed approach, Proc. ICCAD 2003.
4. Y. Zhan et al., Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up, Proc. ASPDAC 2005.
5. K. Skadron et al., Temperature-aware microarchitecture: Modeling and implementation, TACO, 2004.
6. P. Chaparro, J. Gonzalez, G. Magklis, Q. Cai, and A. Gonzalez., Understanding the thermal implications of multi-core architectures., IEEE TPDS, 2007.
7. D. Pham et al., Design and Implementation of a First-Generation Cell Processor., Proc. ISSCC, 2005.
8. P. Kongetira et al., Niagara: A 32-way multithreaded SPARC processor., IEEE Micro, 2005.
9. Tilera Corporation, Tilera's 64-core architecture, www.tilera.com/ products/processors.php, 2007.
10. O. Semenov et al., Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits, IEEE T-D&M, 2006.
11. S. Borkar, Design challenges of technology scaling, IEEE Micro, 1999.
12. D. Brooks et al., Dynamic thermal management for high-performance microprocessors, Proc. HPCA, 2001.
13. C J. Hughes et al., Saving energy with architectural and frequency adaptations for multimedia applications, Proc MICRO, 2001.
14. S. Murali et al., Temperature Control of High Performance Multicore Platforms Using Convex Optimization, Proc. DATE, 2008.
15. J. Donald et al., Techniques for multi-core thermal management: Classif. and new exploration, Proc. ISCA, 2006.
16. D. Atienza et al., HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs, ACM TODAES, 2007.
17. M.-N. Sabry, High-precision compact-thermal models. IEEE Transactions on Components and Packaging Technologies, 2005.
18. A. K. Coskun, et al., Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs, IEEE Transactions on VLSI, vol.16 no.9, pp. 1127-1140, Sept. 2008.
19. F. Zanini, et al., A Control Theory Approach for Thermal Balancing of MPSoC, Proc. ASP-DAC, 2009.
20. Burden Richard L, et al., Numerical Analysis, 7th ed. Belmont, CA: Brooks Cole, 2000.