A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Gangasani, Gautam R ^a   Hsu, Chun Ming ^a   Bulzacchelli, John F ^b   Rylov, Sergey ^b   Beukema, Troy ^b   Freitas, David ^a   Kelly, William ^a   Shannon, Michael ^a   Qi, Jieming ^a   Xu, Hui H ^a   Natonio, Joseph ^a   Rasmus, Todd ^a   Guo, Jong Ru ^a   Wielgos, Michael ^a   Garlett, Jon ^a   Sorna, Michael A ^a   Meghelli, Mounir ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPLANE TRANSCEIVER; BACKPLANES; DATA RATES; DYNAMIC ADAPTATIONS; MULTI-STANDARD; SOI CMOS; TIMING DRIFT; VOLTAGE OFFSETS;

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; TRANSCEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 80455178643     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055366     Document Type: Conference Paper

References (10)

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