A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 348-349

  Quan, Shaolei ^a   Zhong, Freeman ^a   Liu, Wing ^a   Aziz, Pervez ^a   Jing, Tai ^a   Dong, Jen ^a   Desai, Chintan ^a   Gao, Hairong ^a   Garcia, Monica ^a   Hom, Gary ^a   Huynh, Tony ^a   Kimura, Hiroshi ^a   Kothari, Ruchi ^a   Li, Lijun ^a   Liu, Cathy ^a   Lowrie, Scott ^a   Ling, Kathy ^a   Malipatil, Amaresh ^a   Narayan, Ram ^a   Prokop, Tom ^a   Palusa, Chaitanya ^a   Rajashekara, Anil ^a   Sinha, Ashutosh ^a   Zhong, Charlie ^a   Zhang, Eric ^a   more..

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FEEDBACK; INTERSYMBOL INTERFERENCE; OPTICAL CABLES; TRANSCEIVERS;

COPPER CABLES; DATA SAMPLING; IMPEDANCE DISCONTINUITIES; NOISE AMPLIFICATION; OPTICAL MODULES; REFLECTION-INDUCED; ROBUST TRANSCEIVERS; TIMING MARGIN;

DECISION FEEDBACK EQUALIZERS;

EID: 79955720766     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746348     Document Type: Conference Paper

References (6)

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2. Y. Hidaka, et al., "A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control," ISSCC Dig. Tech. Papers, pp. 188-189, Feb., 2009
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4. R. Payne, et al., "A 6.25-Gb/s Binary Transceiver in 0.13um CMOS for Serial Data Transmission across High Loss Legacy Backplane Channels," IEEE J. Solid-State Circuits, vol. 40, pp. 2646-2657, Dec., 2005
5. st-Tap FFE and 3-Tap DFE in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 162-163, Feb., 2010
6. M. Kossel, et al., "A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS with <-16 dB Return Loss over 10 GHz Bandwidth," IEEE J. Solid-State Circuits, vol. 43, pp. 2905-2920, Dec., 2008.