Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 350-351

  Joy, Andrew K ^a   Mair, Hugh ^a   Lee, Hae Chang ^b   Feldman, Arnold ^b   Portmann, Clemenz ^b   Bulman, Neil ^a   Crespo, Eugenia Cordero ^a   Hearne, Peter ^a   Huang, Patty ^b   Kerr, Ben ^a   Khandelwal, Pulkit ^a   Kuhlmann, Franz ^a   Lytollis, Shaun ^a   Machado, Joaquim ^a   Morrison, Casey ^a   Morrison, Scott ^a   Rabii, Shahriar ^b   Rajapaksha, Dushmantha ^a   Ravinuthula, Vishnu ^a   Surace, Giuseppe ^a  

^a TEXAS INSTRUMENTS   (United States)

^b Arda Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

40NM CMOS; BACKPLANES; BAUD RATE; CHANNEL LOSS; DATA RATES; LOW COSTS; NETWORKING SYSTEMS; VOLTAGE MODE;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

EID: 79955709639     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746349     Document Type: Conference Paper

References (5)

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2. K. Fukuda, H. Yamashita, et al, "An 8Gb/s Transceiver with 3x-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane," ISSCC Dig. Tech. Papers, pp. 98-99, Feb. 2008.
3. Y. Hidaka, W. Gai, et al, "A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control," ISSCC Dig. Tech. Papers, pp.188-189, Feb. 2009.
4. W. Dettloff, J. C. Eble, et al, "A 32mW 7.4Gb/s Protocol Agile Source-Series Terminated Transmitter in 45nm CMOS SOI," ISSCC Dig. Tech. Papers, pp. 370-371, Feb. 2010.
5. M. Harwood, N.Warke, et al, "A 12.5Gb/s Serdes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery," ISSCC Dig. Tech. Papers, pp. 436-437, Feb. 2007.