A scalable 3.6-to-5.2mW 5-to-10Gb/s 4-Tap DFE in 32nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 180-181

  Chen, Lidong ^a   Zhang, Xuguang ^a   Spagna, Fulvio ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349266729     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977367     Document Type: Conference Paper

References (4)

1. M. Park, J, Bulzacchelli, M. Beakes, and D. Friedman, "A 7Gb/s 9.3mW 2-Tap Current- Integrating DFE Receiver," ISSCC Dig. Tech. Papers, pp. 230-231, Feb., 2007.
2. T.O. Dickson, J.F. Bulzacchelli, and D.J. Friedman, "A 12-Gb/s 11-mV half-Rate Sampled 5-Tap Decision Feedback Equalizer with Current-Integrating Summer in 45-nm SOI CMOS Technology," IEEE Symp. VLSI Circuits, pp. 58-59, Jun., 2008.
3. R. Payne, P. Landman, B. Bhakta, et al., "A 6.25Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2646-2657, Dec., 2005.
4. K.-L.J. Wong, A.R. Rylyakov, and C.-K.K. Yang, "A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions," IEEE J. Solid-State Circuits, vol.42, no.4, pp. 881-888, Apr., 2007.