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Volumn , Issue , 2003, Pages 801-808

Graphics for the masses: A hardware rasterization architecture for mobile phones

Author keywords

culling; graphics hardware; mobile phone; multisampling; texture filtering

Indexed keywords

CHIP AREAS; CULLING; EXTERNAL MEMORY; GRAPHICS HARDWARE; HARDWARE ARCHITECTURE; HIGH FIDELITY; HIGH QUALITY; MEMORY ACCESS; MEMORY BANDWIDTHS; MULTI-SAMPLING; POWER CONSUMPTION; RASTERIZATION; RASTERIZING; SCANLINE; SMALL DISPLAY; SOFTWARE SIMULATION; TEXTURE COMPRESSION; Z-BUFFER;

EID: 77954016821     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1201775.882348     Document Type: Conference Paper
Times cited : (101)

References (18)
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    • GREENE, N., KASS, M., AND MILLER, G. 1993. Hierarchical Z-Buffer Visibility. In Proceedings of ACM SIGGRAPH 93, ACM Press/ACM SIGGRAPH, New York, J. Kajiya, Ed., Computer Graphics Proceedings, Annual Conference Series, ACM, 231-238.
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    • Kelleher, B.1
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    • ACM Press/ACM SIGGRAPH, New York, E. Fiume, Ed., Computer Graphics Proceedings, Annual Conference Series, ACM
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  • 11
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    • Tiled Polygon Traversal Using Half-Plane Edge Functions
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    • A 120-mW 3-D Rendering Engine with a 6-Mb Embedded DRAM and 3.2 GB/s Runtime Reconfigurable Bus for PDA Chip
    • WOO, R., YOON, C., KOOK, J., LEE, S., AND YOO, H. 2002. A 120-mW 3-D Rendering Engine With a 6-Mb Embedded DRAM and 3.2 GB/s Runtime Reconfigurable Bus for PDA Chip. IEEE Journal of Solid-State Circuits 37, 19 (October), 1352-1355.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.