Implementing homeostatic plasticity in VLSI networks of spiking neurons

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 682-685

  Bartolozzi, Chiara ^a   Nikolayeva, Olga ^b   Indiveri, Giacomo ^b  

^a ISTITUTO ITALIANO DI TECNOLOGIA   (Italy)

^b Institute of Neuroinformatics Zurich   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CIRCUIT SIMULATION; NEURAL NETWORKS; NEURONS; PLASTICITY; VLSI CIRCUITS;

DEVICE MISMATCHES; HOMEOSTATIC CONTROLS; LEARNING MECHANISMS; NEURAL SYSTEMS; ON CHIPS; SPIKING NEURAL NETWORKS; SPIKING NEURONS; SYSTEMATIC CHANGES; TEMPERATURE DRIFTS; VLSI NETWORKS;

NETWORKS (CIRCUITS);

EID: 57849169109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674945     Document Type: Conference Paper

References (19)

1. G. Turrigiano and S. Nelson, "Homeostatic plasticity in the developing nervous system," Nature Reviews Neuroscience, vol. 5, pp. 97-107, February 2004.
2. A. Renart, P. Song, and X.-J. Wang, "Robust spatial working memory through homeostatic synaptic scaling in heterogeneous cortical networks," Neuron, vol. 38, pp. 473-485, May 2003.
3. E. Bienenstock, L. Cooper, and P. Munro, "Theory for the development of neuron selectivity: orientation specificity and binocular interaction in visual cortex," Jour. Neurosci., vol. 2, no. 1, pp. 32-48, 1982. [Online]. Available: http://www.jneurosci.org/cgi/content/abstract/2/1/32
4. L. Abbott and W. Gerstner, "Homeostasis and learning through spiketiming dependent plasticity," 2004.
5. L. Abbott and S. Nelson, "Synaptic plasticity: taming the beast," Nature Neuroscience, vol. 3, pp. 1178-1183, November 2000.
6. J. Triesch, "Synergies between intrinsic and synaptic plasticity mechanisms," Neural Computation, vol. 19, pp. 885-909, 2007.
7. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity," IEEE Transactions on Neural Networks, vol. 17, no. 1, pp. 211-221, Jan 2006.
8. J. Arthur and K. Boahen, "Learning in silicon: Timing is everything," in Advances in Neural Information Processing Systems 18, Y. Weiss, B. Schölkopf, and J. Piatt, Eds. Cambridge, MA: MIT Press, 2006.
9. U. Mallik, R. J. Vogelstein, E. Culurciello, R. Etienne-Cummings, and G. Cauwenberghs, "A real-time spike-domain sensory information processing system," in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 3, 2005, pp. 1919-1922.
10. R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. J. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, "AER building blocks for multi-layer multi-chip neuromorphic vision systems," in Advances in Neural Information Processing Systems, S. Becker, S. Thrun, and K. Obermayer, Eds., vol. 15. MIT Press, Dec 2005.
11. E. Chicca, A. M. Whatley, V Dante, P. Lichtsteiner, T. Delbrück, P. Del Giudice, R. J. Douglas, and G. Indiveri, "A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity," IEEE Transactions on Circuits and Systems 1, Regular Papers, vol. 5, no. 54, pp. 981-993, 2007.
12. T. Y. W. Choi, P. A. Merolla, J. V. Arthur, K. A. Boahen, and B. E. Shi, "Neuromorphic implementation of orientation hypercolumns," IEEE Transactions on Circuits and Systems I, vol. 52, no. 6, pp. 1049-1060, 2005.
13. A. Bofill-i Petit and A. F. Murray, "Synchrony detection and amplification by silicon neurons with STDP synapses," IEEE Transactions on Neural Networks, vol. 15, no. 5, pp. 1296-1304, September 2004.
14. H. Riis and P. Hafliger, "Spike based learning with weak multi-level static memory," in Proceedings of IEEE International Symposium on Circuits and Systems. IEEE, 2004, pp. 393-396.
15. S. Liu and B. Minch, "Silicon synaptic adaptation mechanisms for homeostasis and contrast gain control," IEEE Transactions on Neural Networks, vol. 13, no. 6, pp. 1497-1503, November 2002.
16. C. Bartolozzi and G. Indiveri, "Synaptic dynamics in analog VLSI," Neural Computation, vol. 19, no. 10, pp. 2581-2603, Oct 2007.
17. S. Mitra, G. Indiveri, and S. Fusi, "Learning to classify complex patterns using a VLSI network of spiking neurons," in Advances in Neural Information Processing Systems, B. Schölkopf, J. Platt, and T. Hoffman, Eds. Cambridge (MA): MIT Press, 2007, (In Press).
18. A. G. Andreou, K. A. Boahen, P. O. Pouliquen, A. Pavasovic̀, R. E. Jenkins, and K. Strohbehn, "Current-mode subthreshold MOS circuits for analog VLSI neural system," IEEE Transactions on Neural Networks, vol. 2, no. 2, pp. 205-13, Mar. 1991.
19. N. S. Desai, R. H. Cudmore, S. B. Nelson, and G. Turrigiano, "Critical periods for experience-dependent synaptic scaling in visual cortex," Nature Neuroscience, vol. 5, no. 8, pp. 783-789, August 2002.