-
1
-
-
0004205671
-
-
E.E. Swartzlander (Ed.), Los Alamitos, CA: IEEE Computer Society Press
-
E.E. Swartzlander (Ed.), Computer Arithmetic, Los Alamitos, CA: IEEE Computer Society Press, Vols. 1 & 2, 1990.
-
(1990)
Computer Arithmetic
, vol.1-2
-
-
-
2
-
-
17644373718
-
A Method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
-
March
-
V.G. Oklobdzija, D. Villeger, and S.S. Liu, "A Method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach," IEEE Transactions on Computers, Vol. 45, No. 3, pp. 294-306. March 1996.
-
(1996)
IEEE Transactions on Computers
, vol.45
, Issue.3
, pp. 294-306
-
-
Oklobdzija, V.G.1
Villeger, D.2
Liu, S.S.3
-
3
-
-
0029214183
-
Design strategies for optimal multiplier circuits
-
C. Martels, V.G. Oklobdzija, R. Ravi, and P.F. Stelling, "Design strategies for optimal multiplier circuits," Proceedings of the 12th Symposium on Computer Arithmetic, pp. 42-49, 1995.
-
(1995)
Proceedings of the 12th Symposium on Computer Arithmetic
, pp. 42-49
-
-
Martels, C.1
Oklobdzija, V.G.2
Ravi, R.3
Stelling, P.F.4
-
5
-
-
85013942582
-
Design strategies for the final adder in a parallel multiplier
-
P.F. Stelling and V.G. Oklobdzija, "Design strategies for the final adder in a parallel multiplier," Proceedings of the 29th Asilomar Conference on Signals, Systems, and Computers, pp. 591-595, 1995.
-
(1995)
Proceedings of the 29th Asilomar Conference on Signals, Systems, and Computers
, pp. 591-595
-
-
Stelling, P.F.1
Oklobdzija, V.G.2
-
6
-
-
0026908841
-
Delay optimization of Carry-Skip adders and block Carry-Lookahead adders using multidimensional dynamic programming
-
Aug.
-
P.K. Chan, M.D.F. Schlag, C.D. Thornborson, and V.G. Oklobdzija, "Delay optimization of Carry-Skip adders and block Carry-Lookahead adders using multidimensional dynamic programming," IEEE Transactions on Computers, Vol. 41, No. 8, pp. 920-930, Aug. 1992.
-
(1992)
IEEE Transactions on Computers
, vol.41
, Issue.8
, pp. 920-930
-
-
Chan, P.K.1
Schlag, M.D.F.2
Thornborson, C.D.3
Oklobdzija, V.G.4
-
11
-
-
84940484038
-
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
-
June
-
V.G. Oklobdzija and D. Villeger, "Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology," IEEE Transactions on VLSI Systems, Vol. 3, No. 2, pp. 292-301, June 1995.
-
(1995)
IEEE Transactions on VLSI Systems
, vol.3
, Issue.2
, pp. 292-301
-
-
Oklobdzija, V.G.1
Villeger, D.2
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