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Volumn 14, Issue 3, 1996, Pages 321-331

Design strategies for optimal hybrid final adders in a parallel multiplier

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; GATEWAYS (COMPUTER NETWORKS); OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; SIGNAL PROCESSING;

EID: 0030400560     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00929625     Document Type: Review
Times cited : (30)

References (12)
  • 1
    • 0004205671 scopus 로고
    • E.E. Swartzlander (Ed.), Los Alamitos, CA: IEEE Computer Society Press
    • E.E. Swartzlander (Ed.), Computer Arithmetic, Los Alamitos, CA: IEEE Computer Society Press, Vols. 1 & 2, 1990.
    • (1990) Computer Arithmetic , vol.1-2
  • 2
    • 17644373718 scopus 로고    scopus 로고
    • A Method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
    • March
    • V.G. Oklobdzija, D. Villeger, and S.S. Liu, "A Method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach," IEEE Transactions on Computers, Vol. 45, No. 3, pp. 294-306. March 1996.
    • (1996) IEEE Transactions on Computers , vol.45 , Issue.3 , pp. 294-306
    • Oklobdzija, V.G.1    Villeger, D.2    Liu, S.S.3
  • 6
    • 0026908841 scopus 로고
    • Delay optimization of Carry-Skip adders and block Carry-Lookahead adders using multidimensional dynamic programming
    • Aug.
    • P.K. Chan, M.D.F. Schlag, C.D. Thornborson, and V.G. Oklobdzija, "Delay optimization of Carry-Skip adders and block Carry-Lookahead adders using multidimensional dynamic programming," IEEE Transactions on Computers, Vol. 41, No. 8, pp. 920-930, Aug. 1992.
    • (1992) IEEE Transactions on Computers , vol.41 , Issue.8 , pp. 920-930
    • Chan, P.K.1    Schlag, M.D.F.2    Thornborson, C.D.3    Oklobdzija, V.G.4
  • 11
    • 84940484038 scopus 로고
    • Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
    • June
    • V.G. Oklobdzija and D. Villeger, "Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology," IEEE Transactions on VLSI Systems, Vol. 3, No. 2, pp. 292-301, June 1995.
    • (1995) IEEE Transactions on VLSI Systems , vol.3 , Issue.2 , pp. 292-301
    • Oklobdzija, V.G.1    Villeger, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.