An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 103-106

  Hsu, Steven K ^a   Aqarwal, Amit ^b   Roy, Kaushik ^b   Krishnamurthy, Ram K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

^b Purdue University   (United States)

Author keywords

Dual Vt Vcc; Flip flop; Hot spot; Level converter

Indexed keywords

ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; POWER ELECTRONICS; SWITCHING SYSTEMS;

DUAL VT/VCC; FLIP-FLOP; HOT SPOT; LEVEL CONVERTER;

CMOS INTEGRATED CIRCUITS;

EID: 28444482144     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195495     Document Type: Conference Paper

References (5)

1. S. Thompson et al, "A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell," International Electron Devices Meeting, Dec. 2002.
2. J. Cai et al, "Supply voltage strategies for minimizing the power of CMOS processors," VLSI Tech. Symp. Dig., 2002.
3. S. Vangal et al, "A 25GHz 32b integer-execution core in 130nm dual-Vt CMOS," International Solid-State Circuit Conference (ISSCC) Digest, pp. 412-413, 2002.
4. M. Anders et al, "A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop," International Solid-State Circuit Conference (ISSCC) Digest, 2002.
5. S. Mathew et al., "Sub-500ps 64b ALU's in 0.18μm SOI/bulk CMOS: Design & scaling trends," in Proc. ISSCC Dig. Tech. Papers, Feb. 2001, pp. 318-319.