-
1
-
-
0000793139
-
Cramming more components onto integrated circuits
-
Moore, G.E.: Cramming more components onto integrated circuits. Electron. 38, 114-117 (1965)
-
(1965)
Electron
, vol.38
, pp. 114-117
-
-
Moore, G.E.1
-
2
-
-
84870780322
-
-
available at
-
Information available at: http://www.hpcwire.com/
-
Information
-
-
-
3
-
-
33947323782
-
Silicon Nano-Transistors and Breaking the 10 nm Physical Gate Length Barrier
-
IR-TR-2003-7
-
Chau, R., Doyle, B., Doczy, M., Datta, S., Hareland, S., Jin, B., Kavalieros, J., Metz, M.: Silicon Nano-Transistors and Breaking the 10 nm Physical Gate Length Barrier. Intel Research Technical Report IR-TR-2003-7 (2003)
-
(2003)
Intel Research Technical Report
-
-
Chau, R.1
Doyle, B.2
Doczy, M.3
Datta, S.4
Hareland, S.5
Jin, B.6
Kavalieros, J.7
Metz, M.8
-
4
-
-
0141522968
-
A Little light magic
-
Schellenberg, F.: A Little light magic, IEEE Spect. 40 34-39
-
IEEE Spect
, vol.40
, pp. 34-39
-
-
Schellenberg, F.1
-
5
-
-
0037703966
-
On the diffraction of object glasses
-
Lord Rayleigh, On the diffraction of object glasses. Mon. Not. R. Astron. Soc. 33, 59-63 (1872)
-
(1872)
Mon. Not. R. Astron. Soc
, vol.33
, pp. 59-63
-
-
Rayleigh, L.1
-
6
-
-
84957514431
-
-
Mack, C.A.: Understanding focus effects in submicron optical lithography. In: Optical/Laser Microlithography, Proceedings of the SPIE 922, 135-148 (1988); Opt. Eng. 27(12), 1093-1100 (1988)
-
Mack, C.A.: Understanding focus effects in submicron optical lithography. In: Optical/Laser Microlithography, Proceedings of the SPIE 922, 135-148 (1988); Opt. Eng. 27(12), 1093-1100 (1988)
-
-
-
-
7
-
-
33947316463
-
-
Hopkins, H.H.: On the diffraction theory of optical images. Proc. R. Soc. Lond. A Math. Phys. Sci. 217 (1130), 408-432 (1953)
-
Hopkins, H.H.: On the diffraction theory of optical images. Proc. R. Soc. Lond. A Math. Phys. Sci. 217 (1130), 408-432 (1953)
-
-
-
-
8
-
-
2942640096
-
Forbidden area avoidance with spacing technique for layout optimization
-
Wong, A.K. et al.: Forbidden area avoidance with spacing technique for layout optimization. In: Proceedings of SPIE, vol. 5379, pp. 67-75 (2004)
-
(2004)
Proceedings of SPIE
, vol.5379
, pp. 67-75
-
-
Wong, A.K.1
-
9
-
-
0036030174
-
Understanding the Forbidden Pitch Phenomenon and Assist Feature Placement
-
Shi, X., Hsu, S., Chen, F., Hsu, M., Socha, R., Dusa, M.: Understanding the Forbidden Pitch Phenomenon and Assist Feature Placement. In: Microlithography XVI, Proceedings of the SPIE vol. 4689 (2000)
-
(2000)
Microlithography XVI, Proceedings of the SPIE
, vol.4689
-
-
Shi, X.1
Hsu, S.2
Chen, F.3
Hsu, M.4
Socha, R.5
Dusa, M.6
-
10
-
-
0033712150
-
Forbidden pitches for 130 nm lithograph and below. Optical Microlithography XIII
-
Progler, C.J, ed
-
Socha, R., Dusa, M., Capodieci, L., Finders, J., Chen, F., Flagello, D., Cummings, K.: Forbidden pitches for 130 nm lithograph and below. Optical Microlithography XIII, In: Progler, C.J. (ed). Proceedings of SPIE, vol. 4000, pp. 1140-1155 (2000)
-
(2000)
Proceedings of SPIE
, vol.4000
, pp. 1140-1155
-
-
Socha, R.1
Dusa, M.2
Capodieci, L.3
Finders, J.4
Chen, F.5
Flagello, D.6
Cummings, K.7
-
12
-
-
0002609165
-
A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran
-
Brglez, F., Fujiwara, H.: A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. Proc. IEEE Int. Symp. Circuits Sys. 663-698, pp. 671-674 (1985)
-
(1985)
Proc. IEEE Int. Symp. Circuits Sys
, vol.663-698
, pp. 671-674
-
-
Brglez, F.1
Fujiwara, H.2
-
13
-
-
0042635594
-
-
DAC
-
Pileggi, L., Schmit, H., Strojwas, A.J., Gopalakrishanan, P., Kheterpal, V., Koorapaty, A., Patel, C., Rovner, V., Tong, K.Y.: Exploring regular fabrics to optimize the performance-cost trade-off. Proc. DAC, 782-787 (2003)
-
(2003)
Exploring regular fabrics to optimize the performance-cost trade-off. Proc
, pp. 782-787
-
-
Pileggi, L.1
Schmit, H.2
Strojwas, A.J.3
Gopalakrishanan, P.4
Kheterpal, V.5
Koorapaty, A.6
Patel, C.7
Rovner, V.8
Tong, K.Y.9
-
14
-
-
0242696159
-
Regular logic fabrics for a Via patterned gate array (VPGA)
-
Tong, K.Y., Kheterapal, V., Rovner, S., Schmit, H., Pileggi, L., Puri, R.: Regular logic fabrics for a Via patterned gate array (VPGA). In: Proceedings of the Int'l Custom Integrated Circuits Conference, pp. 53-56 (2003)
-
(2003)
Proceedings of the Int'l Custom Integrated Circuits Conference
, pp. 53-56
-
-
Tong, K.Y.1
Kheterapal, V.2
Rovner, S.3
Schmit, H.4
Pileggi, L.5
Puri, R.6
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