Thermal-aware cell and through-silicon-via co-placement for 3D ICs

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 670-675

  Cong, Jason ^a,b   Luo, Guojie ^a   Shi, Yiyu ^c  

^a Engineering IV   (United States)

^b CALIFORNIA NANOSYSTEMS INSTITUTE   (United States)

^c MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

Author keywords

3D placement; Thermal awareness; TSV distribution

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRONICS PACKAGING; SILICON; TIMING CIRCUITS;

3-D PLACEMENTS; PEAK TEMPERATURES; POWER DISTRIBUTIONS; THERMAL AWARENESS; THERMAL-AWARE; THROUGH-SILICON-VIA; TSV DISTRIBUTION; WIRE LENGTH;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 80052671580     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024876     Document Type: Conference Paper

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