Array architecture for a nonvolatile 3-dimensional cross-point resistance-change memory

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 9, 2011, Pages 2158-2170

  Ou, Elaine ^a   Wong, S Simon ^b  

^a UNIVERSITY OF SYDNEY   (Australia)

^b Stanford University   (United States)

Author keywords

3D; cross point; flash; nonvolatile memory

Indexed keywords

3-DIMENSIONAL; 3D; AREA EFFICIENCY; ARRAY ARCHITECTURE; BIT DENSITY; CIRCUIT FUNCTIONALITY; CIRCUIT TECHNIQUES; CMOS TECHNOLOGY; CROSS-POINT; CROSS-POINT ARRAY; FLASH; LEAKAGE CURRENT EFFECT; MEMORY CHIPS; MEMORY ELEMENT; NAND FLASH; NON-VOLATILE; NON-VOLATILE MEMORIES; NOR FLASH; NOVEL ARCHITECTURE; RANDOM ACCESS; TEST CHIPS;

CMOS INTEGRATED CIRCUITS; FLASH MEMORY; THREE DIMENSIONAL;

MEMORY ARCHITECTURE;

EID: 80052072008     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2148430     Document Type: Article

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