A 50nm 8Gb NAND flash memory with 100MB/s program throughput and 200MB/S DDR interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 426-625

  Nobunaga, Dean ^a   Abedifard, Ebrahim ^a   Roohparvar, Frankie ^a   Lee, June ^a   Yu, Erwin ^a   Vahidimowlavi, Allahyar ^a   Abraham, Michael ^a   Talreja, Sanjay ^b   Sundaram, Rajesh ^b   Rozman, Rod ^b   Vu, Luyen ^a   Chen, Chih Liang ^a   Chandrasekhar, Uday ^a   Bains, Rupinder ^b   Viajedor, Vimon ^a   Mak, William ^a   Choi, Munseork ^a   Udeshi, Darshak ^b   Luo, Michelle ^a   Qureshi, Shahid ^a   Tsai, Jeffrey ^a   Jaffin, Frederick ^a   Liu, Yujiang ^a   Mancinelli, Marco ^a   more..

^a MICRON TECHNOLOGY INC   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; NAND CIRCUITS;

ARRAY EFFICIENCY; DATA RATES; NAND FLASH MEMORY; NAND STRINGS;

MEMORY ARCHITECTURE;

EID: 49549122064     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523239     Document Type: Conference Paper

References (5)

1. 2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput", IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 219-232, Jan. 2007.
2. 2 8Gb Multi-Level NAND Flash Memory with 70nm CMOS Technology", IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 161-169, Jan. 2006.
3. C. Villa, D. Vimercati, S. Schippers et al., "A 65nm 1Gb 2b/CeU NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR Interface", ISSCC Dig. Tech. Papers, pp. 476-477, Feb. 2007.
4. K.-D. Suh, B.-H. Suh, Y-.H. Lim et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme", IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
5. K.-T. Park, J. Choi, J. Sel et al., "A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond", Dig. Symp. VLSI Technology, pp. 19-20, Jun. 2006.