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Volumn 1, Issue 2, 2011, Pages 183-192

Design of subthreshold SRAMs for energy-efficient quality-scalable video applications

Author keywords

embedded; H.264 decoder; SRAM; Subthreshold

Indexed keywords

BITCELL; DESIGN TECHNIQUE; DYNAMIC CIRCUITS; EMBEDDED; ENERGY EFFICIENT; H.264 DECODER; H.264 VIDEO DECODER; MULTI-OUTPUT; OPERATING SPEED; POWER-GATING; SCALABLE VIDEO; SMALL AREA; SRAM MACRO; SUBTHRESHOLD; VIDEO APPLICATIONS;

EID: 80052045920     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2011.2158345     Document Type: Article
Times cited : (21)

References (12)
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    • H. Yamauchi, "A scaling trend of variation-tolerant SRAM circuit design in deeper nano-meter era," J. Semicond. Technol. Sci., pp. 37-50, Mar. 2009.
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    • Yamauchi, H.1
  • 9
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    • A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation
    • DOI 10.1109/JSSC.2006.891726
    • B. H. Calhoun and A. Chandrakasan, "A 256 kb 65 nm sub-threshold SRAM design for ultra-low-voltage operation," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680-688, Mar. 2007. (Pubitemid 46376044)
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.3 , pp. 680-688
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  • 10
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    • I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.2 , pp. 650-658
    • Chang, I.J.1    Kim, J.J.2    Park, S.P.3    Roy, K.4
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    • A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS
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    • M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS," IEEE J. Solid-State Circuit, vol. 44, no. 11, pp. 3163-3173, Nov. 2009.
    • (2009) IEEE J. Solid-State Circuit , vol.44 , Issue.11 , pp. 3163-3173
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.