A discussion on SRAM circuit design trend deeper nano-meter era

s2008 International SoC Design Conference, ISOCC 2008

Volumn 1, Issue , 2008, Pages 164-167

  Yamauchi, Hiroyuki ^a  

^a FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

SRAM; SRAM design solution; SRAM scaling

Indexed keywords

LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE; TIMING CIRCUITS;

AREA OVERHEAD; CELL TOPOLOGY; CIRCUIT DESIGNS; DESIGN SOLUTIONS; MULTIPLE VOLTAGE; SEQUENCE CONTROL; SRAM DESIGN; VT VARIATION;

INTEGRATED CIRCUIT DESIGN;

EID: 69949104514     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2008.4815598     Document Type: Conference Paper

References (4)

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3. K.Itoh, M.Horiguchi, M.Yamaoka "Low-Voltage Limitations of Memory-Rich Nano-Scale CMOS LSIs", 33rd European Solid State Circuits Conference,ESSCIRC 2007, plenary talk, pp.11-13, Sept. 2007
4. A. Kawasumi, N. Otsuka, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A. Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, 21.4 "A Single-Power-Supply 0.7V 1GHz 45nm SRAM with a Asymmetrical Unit-Ratio Memory Cell" IEEE Solid States Circuits Conference 2008,pp.382-383, Feb, 2008