Influence of inversion layer on tunneling field-effect transistors

IEEE Electron Device Letters

Volumn 32, Issue 9, 2011, Pages 1191-1193

  Lee, Woojun ^a   Choi, Wooyoung ^a  

^a Sogang University   (South Korea)

Author keywords

Current degradation; inversion layer; surface potential; tunneling field effect transistor (TFET)

Indexed keywords

BAND TO BAND TUNNELING; CURRENT DEGRADATION; GATE VOLTAGES; INVERSION LAYER; SIMULATION RESULT; SURFACE CHANNEL POTENTIAL; TUNNELING FIELD-EFFECT TRANSISTOR (TFET); TUNNELING FIELD-EFFECT TRANSISTORS;

DRAIN CURRENT; TRANSISTORS;

FIELD EFFECT TRANSISTORS;

EID: 80052021225     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2159257     Document Type: Article

References (12)

1. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007.
2. S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, V. Narayanan, D. Schlom, A. Liu, and S. Datta, "Experimental demonstration of 100 nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications," in IEDM Tech. Dig., Dec. 2009, pp. 949-951.
3. S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, "Germanium-source tunnel field effect transistors with record high ION/IOFF," in VLSI Symp. Tech. Dig., Jun. 2009, pp. 178-179.
4. K. K. Bhuwalka, J. Schulze, and I. Eisele, "A simulation approach to optimize the electrical parameters of a vertical tunnel FET," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1541-1547, Jul. 2005.
5. W. Vandenberghe, A. Verhulst, G. Groeseneken, B. Soree, and W. Magnus, "Analytical model for a tunnel field-effect transistor," in Proc. MELECON, May 2008, pp. 923-928.
6. A. S. Verhulst, B. Soree, D. Leonelli, W. G. Vandenberghe, and G. Groeseneken, "Modeling the single-gate, double-gate, and gate-allaround tunnel field-effect transistor," J. Appl. Phys., vol. 107, no. 2, pp. 024518-1-024518-8, Jan. 2010.
7. C. Shen, S.-L. Ong, C.-H. Heng, G. S. Samudra, and Y.-C. Yeo, "A variational approach to the two-dimensional nonlinear Poisson's equation for the modeling of tunneling transistors," IEEE Electron Device Lett., vol. 29, no. 11, pp. 1252-1255, Nov. 2008.
8. ATLAS User's Manual, SILVACO Int., Santa Clara, CA, 2010.
9. W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, "A novel biasing scheme for I-MOS (impact-ionization MOS) devices," IEEE Trans. Nanotechnol., vol. 4, no. 3, pp. 322-325, May 2005.
10. P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, "Complementary tunneling transistor for low power application," Solid State Electron., vol. 48, no. 12, pp. 2281-2286, Dec. 2004.
11. H.-S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth, "Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFETs," Solid State Electron., vol. 30, no. 9, pp. 953-968, Sep. 1987.
12. K. K. Bhuwalka, S. Sedlmaier, A. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, "Vertical tunnel field-effect transistor," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279-282, Feb. 2004.