Energy-efficient joint scheduling and application-specific interconnection design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 10, 2011, Pages 1813-1822

  Xu, Cathy Qun ^a   Xue, Chun Jason ^b   Sha, Edwin H M ^c,d  

^a ERICSSON RESEARCH   (Sweden)

^b CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^c The University of Texas at Dallas   (United States)

^d HUNAN UNIVERSITY   (China)

Author keywords

high level synthesis; Interconnection network; low power; multiprocessor architecture; network on chip

Indexed keywords

CONSTRAINT FACTOR; DEEP SUBMICROMETER; DYNAMIC ENERGY CONSUMPTION; ENERGY EFFICIENT; ENERGY MINIMIZATION; HIGH LEVEL SYNTHESIS; HIGH PERFORMANCE SYSTEMS; INTERCONNECTION DESIGN; JOINT SCHEDULING; LOW POWER; MEDIA APPLICATION; MULTI PROCESSOR ARCHITECTURE; NETWORK ON CHIP; PERFORMANCE DEGRADATION; SCHEDULING TECHNIQUES; STATIC AND DYNAMIC; STATIC ENERGY;

DATA TRANSFER; DESIGN; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; SCHEDULING ALGORITHMS; SIGNAL PROCESSING; SYSTEMS ANALYSIS;

ENERGY EFFICIENCY;

EID: 80051799019     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2062544     Document Type: Article

References (29)

1. L. Chao, E. H.-M. Sha, and A. LaPaugh, "Rotation scheduling: A loop pipelining algorithm," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 3, pp. 229-239, Mar. 1997. (Pubitemid 127767669)
2. J. Y. Chen, W. Jone, J. S.Wang, H.-I. Lu, and T. F. Chen, "Segmented bus design for low-power systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 1, pp. 25-29, Mar. 1999.
3. W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. DAC, Jun. 2001, pp. 684-689. (Pubitemid 32841038)
4. N. Eisley and L.-S. Peh, "High-level power analysis for on-chip networks," in Proc. CASE, Sep. 2004, pp. 104-115. (Pubitemid 41802772)
5. C. Ewering, "Automatic high level synthesis of partitioned buses," in Proc. ICCAD, 1990, pp. 304-307. (Pubitemid 21675443)
6. P. Faraboschi, G. Brown, J. Fisher, G. Desoll, and F. Homewood, "Lx: A technology platform for customizable vliw embedded processing," in Proc. ISCA, 2000, pp. 203-213.
7. M. Fredman and R. Tarjan, "Fibonacci heaps and their uses in improved network optimization algorithms," J. ACM, vol. 34, no. 3, pp. 596-615, 1987.
8. J. Guo, A. Papanikolaou, and F. Catthoor, "Topology exploration for energy efficient intra-tile communication," in Proc. ASP-DAC, Jan. 2007, pp. 178-183.
9. J. Guo, A. Papanikolaou, P. Marchal, and F. Catthoor, "Physical design implementation of segmented buses to reduce communication energy," in Proc. ASP-DAC, 2006, pp. 42-47. (Pubitemid 44375888)
10. K. Heyrman, A. Papanikolaou, F. Catthoor, P. Veelaert, and W. Phillips, "Energy costs of transporting switch control bits for a segmented bus," in Proc. proRISC, 2005, pp. 359-364.
11. T. Instruments, "TMS320C6000 CPU and instruction set reference guide," Literature No. SPRU189, Jul. 2006.
12. J. Jeon and K. Choi, "Effective synthesis algorithm for partitioned bus architecture," Electron. Lett., vol. 35, no. 6, Mar. 1999.
13. W.-B. Jone, J.Wang, H. Lu, I. Hsu, and J.-Y. Chen, "Design theory and implementation for low-power segmented bus systems," ACM Trans. Des. Autom. Electron. Syst., vol. 8, no. 1, pp. 38-54, Jan. 2003. (Pubitemid 36320983)
14. N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, pp. 68-75, Dec. 2003.
15. R. Kumar, V. Zyuban, and D. M. Tullsen, "Interconnections in multicore architectures: Understanding mechanisms, overheads and scaling," in Proc. ISCA, Jun. 2005, pp. 408-419. (Pubitemid 41543458)
16. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Mediabench: A tool for evaluation and synthesizing multimedia and communications systems," in Proc. Internal Symp. Microarchitecture, 1997, pp. 330-335.
17. J. Lee, K. Choi, and N. Dutt, "Compilation approach for coarse-grained reconfigurable architecture," IEEE Des. Test Comput., vol. 20, no. 1, pp. 26-33, Jan. 2003.
18. C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, no. 1, pp. 6:5-35, Jun. 1991.
19. D. Lewis, D. Galloway, M. Ierssel, J. Rose, and P. Chow, "The transmogrifier- 2: A 1-million gate rapid prototyping system," IEEE Trans. Very Large Scale Integr. Syst., vol. 6, no. 2, pp. 188-198, Jun. 1998.
20. M. Qiu, L. T. Yang, Z. Shao, and E. H.-M. Sha, "Dynamic and leakage energy minimization with soft real-time loop scheduling and voltage assignment," IEEE Trans. Very Large Scale Integr. Syst., vol. 18, no. 3, pp. 501-504, Mar. 2010.
21. V. Raghunathan, M. B. Srivastava, and R. K. Gupta, "A survey of techniques for energy efficient on-chip communication," in Proc. DAC, Jun. 2003, vol. 2, no. 6, pp. 900-905.
22. T. Seceleanu, V. Leppanen, and O. Nevalainen, "Device allocation on the segbus platform based on communication scheduling cost minimization," in Proc. IEEE Int. SOC Conf., 2007, pp. 191-196.
23. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli, "Addressing the system-on-a-chip interconnect woes through communication-based design," in Proc. DAC, Jun. 2001, pp. 667-672. (Pubitemid 32841035)
24. S. Sriram and S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization. New York: Marcel Dekker, 2000.
25. C. Xu, C. Xue, J. Hu, and E. H.-M. Sha, "Optimizing scheduling and inter-cluster connection for application specific dsp processors," IEEE Trans. Signal Process., vol. 57, no. 11, pp. 4538-4547, Nov. 2009.
26. C. Xue, J. Hu, Z. Shao, and E. H.-M. Sha, "Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding," ACM Trans. Embedded Comput. Syst., vol. 9, no. 3, pp. 1-26, Feb. 2010.
27. C. Xue, Z. Jia, Z. Shao, M. Wang, and E. H.-M. Sha, "Optimized address assignment with array and loop transformations for minimizing schedule length," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 379-389, Feb. 2008. (Pubitemid 351618431)
28. C. Xue, Z. Shao, Q. Zhuge, B. Xiao, M. Liu, and E. H.-M. Sha, "Optimizing address assignment for scheduling DSPs with multiple functional units," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 9, pp. 976-980, Sep. 2006. (Pubitemid 46511490)
29. V. Zivojnovic, J. Martinez, C. Schlager, and H. Meyr, "Dspstone: A dsporiented benchmarking methodology," in Proc. Internal Conf. Signal Process. Appl. Technol., Oct. 1994, pp. 715-720.