Design theory and implementation for low-power segmented bus systems

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 1, 2003, Pages 38-54

  Jone, W B ^a   Wang, J S ^b   Lu, Hsueh I ^c   Hsu, I P ^d   Chen, J Y ^e  

^a UNIVERSITY OF CINCINNATI   (United States)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^c INSTITUTE OF INFORMATION SCIENCE   (Taiwan)

^d FARADAY TECHNOLOGY CORPORATION   (Taiwan)

^e WINBOND ELECTRONICS CORPORATION   (Taiwan)

Author keywords

ASIC design; Bus graph model; Bus segmentation; Bus segmentation cell; Low power design; Low power design flow; OLA tree

Indexed keywords

BUS SEGMENTATION;

ALGORITHMS; CAPACITANCE; COMMUNICATION SYSTEMS; POWER CONTROL; SWITCHING; TREES (MATHEMATICS);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0037218782     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/606603.606606     Document Type: Article

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