메뉴 건너뛰기




Volumn , Issue , 2011, Pages 217-223

Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; COMPARATIVE STUDIES; DATA PATHS; DATA RATES; ELECTRICAL MODELING; EYE DIAGRAMS; FREQUENCY AND TIME DOMAINS; HIGH BANDWIDTH; LOGIC IC; LOWER COST; LOWER-POWER CONSUMPTION; MEMORY CAPACITY; MOBILE APPLICATIONS; PACKAGE CONFIGURATIONS; SIGNAL PATHS; THIN GLASS; ULTRA-HIGH; ULTRA-THIN;

EID: 79960430006     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898516     Document Type: Conference Paper
Times cited : (52)

References (18)
  • 2
    • 79251589652 scopus 로고    scopus 로고
    • Development of super thin tsv pop
    • F. Carson et al., "Development of super thin tsv pop", in CPMT Symposium Japan, 2010 IEEE, 2010, pp. 1-4.
    • (2010) CPMT Symposium Japan, 2010 IEEE , pp. 1-4
    • Carson, F.1
  • 3
    • 79960428848 scopus 로고    scopus 로고
    • Next generation PoP for processor and memory stacking
    • Tessera, "Next generation PoP for Processor and Memory stacking", ECN.
    • ECN
    • Tessera1
  • 4
    • 70349658299 scopus 로고    scopus 로고
    • Development of through silicon via (tsv) interposer technology for large die (21 x 21mm) fine-pitch cu/low-k fcbga package
    • May
    • X. Zhang et al., "Development of through silicon via (tsv) interposer technology for large die (21 x 21mm) fine-pitch cu/low-k fcbga package", in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, May 2009, pp. 305-312.
    • (2009) Electronic Components and Technology Conference, 2009. ECTC 2009. 59th , pp. 305-312
    • Zhang, X.1
  • 8
    • 68949175484 scopus 로고    scopus 로고
    • Vertical integration of stacked dram and high-speed logic device using smafti technology
    • Y. Kurita et al., "Vertical integration of stacked dram and high-speed logic device using smafti technology", Advanced Packaging, IEEE Transactions on, vol. 32, no. 3, pp. 657-665, 2009.
    • (2009) Advanced Packaging, IEEE Transactions on , vol.32 , Issue.3 , pp. 657-665
    • Kurita, Y.1
  • 9
    • 77951243903 scopus 로고    scopus 로고
    • An industrial perspective of 3d ic integration technology from the viewpoint of design technology
    • K.-M. Choi, "An industrial perspective of 3d ic integration technology from the viewpoint of design technology", in Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, 2010, pp. 544-547.
    • (2010) Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific , pp. 544-547
    • Choi, K.-M.1
  • 10
    • 34748889075 scopus 로고    scopus 로고
    • Challenges for 3d ic integration: Bonding quality and thermal management
    • P. Leduca et al., "Challenges for 3d ic integration: bonding quality and thermal management", in International Interconnect Technology Conference, IEEE 2007, 2007, pp. 210-212.
    • (2007) International Interconnect Technology Conference, IEEE 2007 , pp. 210-212
    • Leduca, P.1
  • 11
    • 70350607965 scopus 로고    scopus 로고
    • Test challenges for 3d integrated circuits
    • H. Lee and K. Chakrabarty, "Test challenges for 3d integrated circuits", Design Test of Computers, IEEE, vol. PP, no. 99, p. 1, 2009.
    • (2009) Design Test of Computers, IEEE , vol.PP , Issue.99 , pp. 1
    • Lee, H.1    Chakrabarty, K.2
  • 13
    • 79960434821 scopus 로고    scopus 로고
    • JEDEC
    • JEDEC, "PoP standards", www.jedec.com.
    • PoP Standards
  • 14
    • 79960426887 scopus 로고    scopus 로고
    • Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias
    • V. Sukumaran et al., "Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias", in Electronic Components and Technology Conference (ECTC), 2011 Proceedings 61th, 2011, pp. 557-563.
    • (2011) Electronic Components and Technology Conference (ECTC), 2011 Proceedings 61th , pp. 557-563
    • Sukumaran, V.1
  • 17
    • 46049089466 scopus 로고    scopus 로고
    • A 3d packaging technology for 4 gbit stacked dram with 3 gbps data transfer
    • M. Kawano et al., "A 3d packaging technology for 4 gbit stacked dram with 3 gbps data transfer", in Electron Devices Meeting, 2006. IEDM'06. International, 2006, pp. 1-4.
    • (2006) Electron Devices Meeting, 2006. IEDM'06. International , pp. 1-4
    • Kawano, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.