Hermetic wafer-level packaging development for RF MEMS switch

Electronics System Integration Technology Conference, ESTC 2010 - Proceedings

Volumn , Issue , 2010, Pages

  Ferrandon, C ^a   Greco, F ^a   Lagoutte, E ^a   Descours, P ^a   Enyedy, G ^a   Pellat, M ^a   Gillot, C ^a   Rey, P ^a   Mercier, D ^a   Cueff, M ^a   Baillin, X ^a   Perruchot, F ^a   Sillon, N ^a   Liu, L J ^b   Pacheco, S ^b   Miller, M ^b  

^a CEA LETI   (France)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROLLED ATMOSPHERE; EDX ANALYSIS; ELECTRICAL CONNECTION; ELECTROSTATIC HOLD; EUTECTIC BONDING; EVALUATION TEST; HERMETIC SEALING; HERMETICITY; LEAK RATE; LOW TEMPERATURES; MAIN PROCESS; MOVING CONTACT; MOVING PARTS; PACKAGING PROCESS; PIEZOELECTRIC ACTUATION; PROCESS FLOWS; RF-MEMS SWITCHES; SEM; SHEAR TESTS; SN BUMPS; SOLDER MATERIAL; VIA RESISTANCE; WAFER LEVEL; WAFER LEVEL PACKAGING; XPS;

ATMOSPHERIC PRESSURE; DIELECTRIC MATERIALS; ELECTRIC CONNECTORS; ELECTRIC SWITCHES; ELECTROSTATICS; GOLD; PACKAGING MATERIALS; SEALING (CLOSING); SILICON WAFERS; TIN; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 78651345596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2010.5642954     Document Type: Conference Paper

References (10)

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