Failure analysis and process improvement for through silicon via interconnects

Materials Research Society Symposium Proceedings

Volumn 1156, Issue , 2009, Pages 155-162

  Majeed, Bivragh ^a   Van Cauwenberghe, Marc ^a   Tezcan, Deniz S ^a   Soussan, Philippe ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DRY ETCHING; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; PROCESS ENGINEERING; SILICON WAFERS;

DIELECTRIC ETCHING; ELECTRICAL INTERCONNECTIONS; ENABLING TECHNOLOGIES; OPTIMIZED PARAMETER; PROCESS IMPROVEMENT; THROUGH SILICON VIAS; THROUGH-SILICON-VIA; WAFER LEVEL PACKAGING;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 77649138883     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-1156-d08-04-f06-04     Document Type: Conference Paper

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