A study for 0.18um high-density MRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 22-23

  Motoyoshi, M ^a   Yamamura, I ^a   Ohtsuka, W ^a   Shouji, M ^a   Yamagishi, H ^a   Nakamura, M ^a   Yamada, H ^a   Tai, K ^a   Kikutani, T ^a   Sagara, T ^a   Moriyama, K ^a   Mori, H ^a   Fukumoto, C ^a   Watanabe, M ^a   Hachino, H ^a   Kano, H ^a   Bessho, K ^a   Narisawa, H ^a   Hosomi, M ^a   Okazaki, N ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING; DURABILITY; ELECTRIC RESISTANCE; MAGNETIC STORAGE; MAGNETORESISTANCE; OPTIMIZATION; SCANNING ELECTRON MICROSCOPY; SWITCHING CIRCUITS; TRANSMISSION ELECTRON MICROSCOPY;

MAGNETIC TUNNEL JUNCTIONS (MTJ); MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM); SIGMA SEPARATION;

RANDOM ACCESS STORAGE;

EID: 4544278338     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Durlam et. al., IEDM Tech. Dig., pp. 995-997, 2003.
2. S. Tehrani et. al., IEEE Trans. Mags., 36, pp. 2752-2757, 2000.
3. A.Bette et. al., Symposium on VLSI circuits, pp.217-220, 2003.
4. I. G Baek et. al., IEDM Tech. Dig., pp831-834, 2003.
5. N. D. Rizzo et. al., Appl. Phys. Lett, 80, pp.2335-2337, 2002.