Optimizing simulated annealing on GPU: A case study with IC floorplanning

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Volumn , Issue , 2011, Pages 263-269

  Han, Yiding ^a   Roy, Sanghamitra ^a   Chakraborty, Koushik ^a  

^a Utah State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOOR-PLANNING; FLOORPLANS; PERFORMANCE OPTIMIZATIONS; SEQUENTIAL ALGORITHM; SINGLE INSTRUCTION MULTIPLE DATA; SOLUTION QUALITY; SOLUTION SPACE;

ALGORITHMS; BENCHMARKING; PROGRAM PROCESSORS; SEQUENTIAL SWITCHING;

SIMULATED ANNEALING;

EID: 79959197523     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2011.5770735     Document Type: Conference Paper

References (17)

1. ADYA, S. N., AND MARKOV, I. Fixed-outline floorplanning: enabling hierarchical design. IEEE Trans. on VLSI Systems. 11, 6 (2003).
2. CHANG, Y.-C., CHANG, Y.-W., WU, G.-M., AND WU, S.-W. B*-trees: a new representation for non-slicing floorplans. In Proceedings of the 37th Design Automation Conference (2000).
3. CHATTERJEE, D., DEORIO, A., AND BERTACCO, V. Event-driven gatelevel simulation with GP-GPUs. In Proc. of 46th Proc. of DAC (2009).
4. CHEN, T.-C., AND CHANG, Y.-W. Modern floorplanning based on B*-tree and fast simulated annealing. TCAD 25, 4 (2006), 637-650.
5. CHEN, T.-C., CHANG, Y.-W., AND LIN, S.-C. IMF: int erconnectdriven multilevel floorplanning for large-scale building-module designs. In Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design (2005), pp. 159-164. (Pubitemid 44815711)
6. CONG, J., AND ZOU, Y. Parallel multi-level analytical global placement on graphics processing units. In Proc. of ICCAD (2009).
7. DENG, Y., WANG, B. D., AND MU, S. Taming irregular EDA applications on GPUs. In Proc. of ICCAD (2009).
8. FENG, Z., AND LI, P. Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms. In Proc. of ICCAD (2008).
9. FRISHMAN, Y., AND TAL, A. Multi-Level Graph Layout on the GPU. IEEE Trans. Vis.Comput. Graph. 13, 6 (2007), 1310-1319.
10. FRISHMAN, Y., AND TAL, A. Online Dynamic Graph Drawing. IEEE Trans. Vis.Comput. Graph. 14, 4 (2008), 727-740. (Pubitemid 351780202)
11. GULATI, K., AND KHATRI, S. Towards Acceleration of Fault Simulation using Graphics Processing Units. In Proc. of 45th Proc. of DAC (2008).
12. GUO, P.-N., CHENG, C.-K., AND YOSHIMURA, T. An 0-Tree Representation of Non-Slicing Floorplan and Its Applications. In Proceedings of the 36th Design Automation Conference (1999).
13. KRAVITZ, S. A., AND RUTENBAR, R. A. Multiprocessor-based placement by simulated annealing. In Proceedings of the 23rd ACM/IEEE Design Automation Conference (1986).
14. LIU, Y., AND HU, J. GPU-based parallelization for fast circuit optimization. In Proc. of 46th Proc. of DAC (2009).
15. RAM, D. J., SREENIVAS, T. H., AND SUBRAMANIAM, K. G. Parallel simulated annealing algorithms. Journal of Parallel and Distributed Computing 37, 2 (1996).
16. ROSE, J. S., SNELGROVE, W. M., AND VRANESIC, Z. G. Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, 3 (1988).
17. SHI, J., CAI, Y., HOU, W., MA, L., TAN, S. X., HO, P.-H., AND WANG, X. GPU friendly fast Poisson solver for structured power grid network analysis. In Proc. of 46th Proc. of DAC (2009).