Parallel multi-level analytical global placement on graphics processing units

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 681-688

  Cong, Jason ^a   Zou, Yi ^a  

^a University of California   (United States)

Author keywords

Circuit placement; Co processor acceleration; GPU

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER GRAPHICS; PROGRAM PROCESSORS;

CIRCUIT PLACEMENT; GLOBAL PLACEMENTS; MASSIVELY PARALLELS; MULTILEVELS; PERFORMANCE TUNING; PROGRAMMABILITY; SOFTWARE IMPLEMENTATION; STATE OF THE ART;

GRAPHICS PROCESSING UNIT;

EID: 76349116049     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687525     Document Type: Conference Paper

References (22)

1. ICCAD04 mixed-size placement benchmarks. URL http://vlsicad.eecs.umich. edu/BK/ICCAD04bench/.
2. ISPD'06 placement contest benchmark. URL http://www.sigda.org/ispd2006/ contest.html.
3. Peko suite, placement example with known optimal wirelength. URL http://cadlab.cs.ucla.edu/~pubbench/placement/.
4. Peku suite, placement example with known upperbound of wirelength. URL http://cadlab.cs.ucla.edu/~pubbench/peku.htm.
5. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov. Unification of partitioning, placement and floorplanning. In ICCAD '04: Proc. International Conference on Computer-Aided Design, pages 550-557, 2004.
6. A. E. Caldwell, A. B. Kahng, and I. L. Markov. Can recursive bisection alone produce routable placements? In DAC '00: Proc. Design Automation Conference, pages 477-482, 2000.
7. B. Catanzaro, K. Keutzer, and B.-Y. Su. Parallelizing CAD: a timely research agenda for EDA. In DAC '08: Proc. Design Automation Conference, pages 12-17, 2008.
8. T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In ISPD '05: Proc. International Symposium on Physical Design, pages 185-192, 2005.
9. J. A. Chandy and P. Banerjee. A parallel circuit-partitioned algorithm for timing-driven standard cell placement. J. Parallel Distrib. Comput., 57(1):64-90, 1999.
10. J. Cong. Timing closure based on physical hierarchy. In ISPD '02: Proc. International Symposium on Physical Design, pages 170-174, 2002.
11. J. Cong, G. Luo, and E. Radke. Highly efficient gradient computation for density-constrained analytical placement. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(12):2133-2144, 2008.
12. P. J. Davis and P. Rabinowitz. Methods of Numerical Integration: Second Edition. Dover Publications, November 2007.
13. H. Eisenmann and F. M. Johannes. Generic global placement and floorplanning. In DAC '98: Proc. Design Automation Conference, pages 269-274, 1998.
14. G. Flach, M. Johann, R. Hentschke, and R. Reis. Cell placement on graphics processing units. In SBCCI '07: Proc. Annual Conference on Integrated Circuits and Systems Design, pages 87-92, 2007.
15. M. Harris. Optimizing parallel reduction in CUDA. URL http://developer.download.nvidia.com/ compute/cuda/1-1/Website/projects/ reduction/ doc/reduction.pdf.
16. A. B. Kahng, S. Reda, and Q. Wang. Aplace: a general analytic placement framework. In ISPD '05: Proc. International Symposium on Physical Design, pages 233-235, 2005.
17. A. Ludwin, V. Betz, and K. Padalia. High-quality, deterministic parallel placement for FPGAs on commodity hardware. In FPGA '08: Proc. International Symposium on Field Programmable Gate Arrays, pages 14-23, 2008.
18. J. Markoul. A fast cosine transform in one and two dimensions. IEEE Trans. Acoust., Speech Signal Process, 28(1):27-34, 1980.
19. G.-J. Nam and J. Cong. Modern Circuit Placement, Best Practices and Results. Springer, New York, 2007.
20. C. Sechen and A. Sangiovanni-Vincentelli. TimberWolf3.2: a new standard cell placement and global routing package. In DAC '86: Proc. Design Automation Conference, pages 432-439, 1986.
21. N. Viswanathan and C. C.-N. Chu. FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In ISPD '04: Proc. International Symposium on Physical Design, pages 26-33, 2004.
22. M. Wang, X. Yang, and M. Sarrafzadeh. Dragon2000: standard-cell placement tool for large industry circuits. In ICCAD '00: Proc. International Conference on Computer-Aided Design, pages 260-263, 2000.