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Volumn , Issue , 2009, Pages 943-946

GPU-based parallelization for fast circuit optimization

Author keywords

GPU; Parallel computing; VLSI circuit optimization

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; COMPUTER GRAPHICS; COMPUTER GRAPHICS EQUIPMENT; GATES (TRANSISTOR); PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; THRESHOLD VOLTAGE; TIMING CIRCUITS; VLSI CIRCUITS;

EID: 70350712411     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1630153     Document Type: Conference Paper
Times cited : (22)

References (11)
  • 1
    • 70350731816 scopus 로고    scopus 로고
    • J. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Krüger, A. Lefohn, T. Purcell. A Survey of General-Purpose Computation on Graphics Hardware. In Proceedings of Eurographics, 2005.
    • J. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Krüger, A. Lefohn, T. Purcell. A Survey of General-Purpose Computation on Graphics Hardware. In Proceedings of Eurographics, 2005.
  • 2
    • 51549120204 scopus 로고    scopus 로고
    • Towards Acceleration of Fault Simulation using Graphics Processing Units
    • K. Gulati and S. Khatri. Towards Acceleration of Fault Simulation using Graphics Processing Units. In Proceedings of the ACM/IEEE DAC, 2008.
    • (2008) Proceedings of the ACM/IEEE DAC
    • Gulati, K.1    Khatri, S.2
  • 3
    • 57849103463 scopus 로고    scopus 로고
    • Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms
    • Z. Feng and P. Li. Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms. In Proceedings of the ACM/IEEE ICCAD, 2008.
    • (2008) Proceedings of the ACM/IEEE ICCAD
    • Feng, Z.1    Li, P.2
  • 4
    • 0031335168 scopus 로고    scopus 로고
    • Gate sizing for constrained delay/power/area optimization
    • O. Coudert. Gate sizing for constrained delay/power/area optimization. In IEEE Trans. VLSI, 1997.
    • (1997) IEEE Trans. VLSI
    • Coudert, O.1
  • 5
    • 0033100297 scopus 로고    scopus 로고
    • Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Application
    • L. Wei, Z. Chen, K. Roy and V. De. Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Application. In IEEE Trans. VLSI, 1999.
    • (1999) IEEE Trans. VLSI
    • Wei, L.1    Chen, Z.2    Roy, K.3    De, V.4
  • 7
    • 57849092664 scopus 로고    scopus 로고
    • PaRS: Fast and Near-Optimal Grid-Based Cell Sizing for Library-Based Design
    • T. Wu and A. Davoodi. PaRS: Fast and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. In Proceedings of the ACM/IEEE ICCAD, 2008.
    • (2008) Proceedings of the ACM/IEEE ICCAD
    • Wu, T.1    Davoodi, A.2
  • 8
    • 70349085774 scopus 로고    scopus 로고
    • Y. Liu and J. Hu. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. In Proceedings of the ACM ISPD, 2009.
    • Y. Liu and J. Hu. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. In Proceedings of the ACM ISPD, 2009.
  • 9
    • 70350736787 scopus 로고
    • Buffer Placement in Distributed RC-Tree Networks for minimal Elmore Delay
    • L.P.P.P. van Ginneken. Buffer Placement in Distributed RC-Tree Networks for minimal Elmore Delay. In IEEE ISCS, 1990.
    • (1990) IEEE ISCS
    • van Ginneken, L.P.P.P.1
  • 10
    • 1542359159 scopus 로고    scopus 로고
    • Minimizion of Dynamic and Static Power Through Joint Assignement of Threshold Voltages and Sizing Optimization
    • D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson and K. Keutzer. Minimizion of Dynamic and Static Power Through Joint Assignement of Threshold Voltages and Sizing Optimization. In ISLPED, 2003.
    • (2003) ISLPED
    • Nguyen, D.1    Davare, A.2    Orshansky, M.3    Chinnery, D.4    Thompson, B.5    Keutzer, K.6
  • 11
    • 70350710826 scopus 로고    scopus 로고
    • NVIDIA CUDA homepage. http://www.nvidia.com/object/cude-home.html.
    • NVIDIA CUDA homepage. http://www.nvidia.com/object/cude-home.html.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.