-
1
-
-
70350731816
-
-
J. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Krüger, A. Lefohn, T. Purcell. A Survey of General-Purpose Computation on Graphics Hardware. In Proceedings of Eurographics, 2005.
-
J. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Krüger, A. Lefohn, T. Purcell. A Survey of General-Purpose Computation on Graphics Hardware. In Proceedings of Eurographics, 2005.
-
-
-
-
2
-
-
51549120204
-
Towards Acceleration of Fault Simulation using Graphics Processing Units
-
K. Gulati and S. Khatri. Towards Acceleration of Fault Simulation using Graphics Processing Units. In Proceedings of the ACM/IEEE DAC, 2008.
-
(2008)
Proceedings of the ACM/IEEE DAC
-
-
Gulati, K.1
Khatri, S.2
-
3
-
-
57849103463
-
Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms
-
Z. Feng and P. Li. Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms. In Proceedings of the ACM/IEEE ICCAD, 2008.
-
(2008)
Proceedings of the ACM/IEEE ICCAD
-
-
Feng, Z.1
Li, P.2
-
4
-
-
0031335168
-
Gate sizing for constrained delay/power/area optimization
-
O. Coudert. Gate sizing for constrained delay/power/area optimization. In IEEE Trans. VLSI, 1997.
-
(1997)
IEEE Trans. VLSI
-
-
Coudert, O.1
-
5
-
-
0033100297
-
Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Application
-
L. Wei, Z. Chen, K. Roy and V. De. Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Application. In IEEE Trans. VLSI, 1999.
-
(1999)
IEEE Trans. VLSI
-
-
Wei, L.1
Chen, Z.2
Roy, K.3
De, V.4
-
6
-
-
0032688692
-
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
-
S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda and D. Blaauw. Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing. In Proceedings of the ACM/IEEE DAC, 1999.
-
(1999)
Proceedings of the ACM/IEEE DAC
-
-
Sirichotiyakul, S.1
Edwards, T.2
Oh, C.3
Zuo, J.4
Dharchoudhury, A.5
Panda, R.6
Blaauw, D.7
-
7
-
-
57849092664
-
PaRS: Fast and Near-Optimal Grid-Based Cell Sizing for Library-Based Design
-
T. Wu and A. Davoodi. PaRS: Fast and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. In Proceedings of the ACM/IEEE ICCAD, 2008.
-
(2008)
Proceedings of the ACM/IEEE ICCAD
-
-
Wu, T.1
Davoodi, A.2
-
8
-
-
70349085774
-
-
Y. Liu and J. Hu. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. In Proceedings of the ACM ISPD, 2009.
-
Y. Liu and J. Hu. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. In Proceedings of the ACM ISPD, 2009.
-
-
-
-
9
-
-
70350736787
-
Buffer Placement in Distributed RC-Tree Networks for minimal Elmore Delay
-
L.P.P.P. van Ginneken. Buffer Placement in Distributed RC-Tree Networks for minimal Elmore Delay. In IEEE ISCS, 1990.
-
(1990)
IEEE ISCS
-
-
van Ginneken, L.P.P.P.1
-
10
-
-
1542359159
-
Minimizion of Dynamic and Static Power Through Joint Assignement of Threshold Voltages and Sizing Optimization
-
D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson and K. Keutzer. Minimizion of Dynamic and Static Power Through Joint Assignement of Threshold Voltages and Sizing Optimization. In ISLPED, 2003.
-
(2003)
ISLPED
-
-
Nguyen, D.1
Davare, A.2
Orshansky, M.3
Chinnery, D.4
Thompson, B.5
Keutzer, K.6
-
11
-
-
70350710826
-
-
NVIDIA CUDA homepage. http://www.nvidia.com/object/cude-home.html.
-
NVIDIA CUDA homepage. http://www.nvidia.com/object/cude-home.html.
-
-
-
|