Multilevel granularity parallelism synthesis on FPGAs

Proceedings - IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011

Volumn , Issue , 2011, Pages 178-185

  Papakonstantinou, Alexandros ^a   Liang, Yun ^b   Stratton, John A ^a   Gururaj, Karthik ^c   Chen, Deming ^a   Hwu, Wen Mei W ^a   Cong, Jason ^c  

^a University of Illinois at Urbana Champaign   (United States)

^b ADVANCED DIGITAL SCIENCES CENTER   (Singapore)

^c Department of Civil and Environmental Engineering   (United States)

Author keywords

Design Space Exploration; FPGA; High Level Sytnthesis; Parallel Computing

Indexed keywords

ABSTRACTION LEVEL; CLOCK PERIOD; COARSE-GRAINED; COMPUTING DOMAIN; DESIGN LAYOUT; DESIGN SPACE EXPLORATION; DESIGN SPACES; EFFICIENT DESIGNS; ENERGY COST; ESTIMATION MODELS; EXECUTION CYCLES; HIGH-LEVEL SYNTHESIS; HIGH-LEVEL SYTNTHESIS; LOGIC SYNTHESIS; MULTI-GRANULARITY; NET LIST; PARALLELISM EXTRACTION; PERFORMANCE EVALUATION; PHYSICAL DESIGN; RECENT PROGRESS; RECONFIGURABLE COMPUTING; SOURCE CODES; SPATIAL PARALLELISM;

COMPUTERS; HEURISTIC ALGORITHMS; LOGIC DESIGN; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; SPACE RESEARCH;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79958742174     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2011.29     Document Type: Conference Paper

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