Design space pruning through early estimations of area/delay tradeoffs for FPGA implementations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 1950-1968

  Bilavarn, Sebastien ^b   Gogniat, Guy ^a,c   Philippe, Jean Luc ^c   Bossuet, Lilian ^d  

^a IEEE   (France)

^b EPFL   (Switzerland)

^c UNIVERSITÉ DE BRETAGNE SUD   (France)

^d UNIVERSITÉ BORDEAUX 1   (France)

Author keywords

Architectural synthesis; Area and delay estimation; C specification; Design space exploration (DSE); Field programmable gate array (FPGA) device; Graph scheduling; Hierarchical control and data flow graph (H CDFG) representation; Technology projection

Indexed keywords

ARCHITECTURAL SYNTHESIS; AREA AND DELAY ESTIMATION; C SPECIFICATIONS; DESIGN SPACE EXPLORATION (DSE); GRAPH SCHEDULING; HIERARCHICAL CONTROL AND DATA FLOW GRAPH (H/CDFG) REPRESENTATION; TECHNOLOGY PROJECTION;

C (PROGRAMMING LANGUAGE); COMPUTATIONAL COMPLEXITY; CONFORMAL MAPPING; FEEDBACK; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SCHEDULING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33748323315     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.862742     Document Type: Article

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