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Volumn , Issue , 2009, Pages 282-287

A computing origami: Folding streams in FPGAs

Author keywords

FPGA; Latency; Streaming; Throughput

Indexed keywords

CUSTOM HARDWARES; FPGA; INHERENT PARALLELISM; LATENCY; LATENCY CONSTRAINTS; NON-TRIVIAL; PERFORMANCE REQUIREMENTS; STREAM PROCESSING; STREAMING; STREAMING APPLICATIONS;

EID: 70350707904     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (42)

References (12)
  • 1
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    • S. Bhattacharyya, P. Murthy, and E. Lee. Kluwer Academic Press, 1996.
    • S. Bhattacharyya, P. Murthy, and E. Lee. Kluwer Academic Press, 1996.
  • 2
    • 34547423880 scopus 로고    scopus 로고
    • Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
    • M. Gordon, W. Thies, and S. Amarasinghe. Exploiting coarse-grained task, data, and pipeline parallelism in stream programs. In ASPLOS'06.
    • ASPLOS'06
    • Gordon, M.1    Thies, W.2    Amarasinghe, S.3
  • 4
    • 4544317363 scopus 로고    scopus 로고
    • Input data reuse in compiling window operations onto reconfigurable hardware
    • Z. Guo, B. Buyukkurt, and W. Najjar. Input data reuse in compiling window operations onto reconfigurable hardware. SIGPLAN Not., 39(7):249-256, 2004.
    • (2004) SIGPLAN Not , vol.39 , Issue.7 , pp. 249-256
    • Guo, Z.1    Buyukkurt, B.2    Najjar, W.3
  • 6
    • 57349172999 scopus 로고    scopus 로고
    • Orchestrating the execution of stream programs on multicore platforms
    • M. Kudlur, , and S. Mahlke. Orchestrating the execution of stream programs on multicore platforms. In PLDI '08.
    • PLDI '08
    • Kudlur, M.1    Mahlke, S.2
  • 7
    • 84944403811 scopus 로고    scopus 로고
    • Single-isa heterogeneous multi-core architectures: The potential for processor power reduction
    • R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen. Single-isa heterogeneous multi-core architectures: The potential for processor power reduction. In MICRO '03.
    • MICRO '03
    • Kumar, R.1    Farkas, K.2    Jouppi, N.3    Ranganathan, P.4    Tullsen, D.5
  • 9
    • 34548348869 scopus 로고    scopus 로고
    • Clock-frequency assignment for multiple clock domain systems-on-a-chip
    • S. Sirowy, Y. Wu, S. Lonardi, and F. Vahid. Clock-frequency assignment for multiple clock domain systems-on-a-chip. In DATE'07.
    • DATE'07
    • Sirowy, S.1    Wu, Y.2    Lonardi, S.3    Vahid, F.4
  • 12
    • 85086525966 scopus 로고    scopus 로고
    • Evaluating heuristics in automatically mapping multi-loop applications to fpgas
    • H. Ziegler and M. Hall. Evaluating heuristics in automatically mapping multi-loop applications to fpgas. In FPGA'05.
    • FPGA'05
    • Ziegler, H.1    Hall, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.