FARM: Fault-aware resource management in NoC-based multiprocessor platforms

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 673-678

  Chou, Chen Ling ^a   Marculescu, Radu ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MAPPING; COMMUNICATION ENERGY; ENTIRE SYSTEM; FAULT-TOLERANT; INTERMITTENT FAULT; MULTI-PROCESSOR PLATFORMS; NETWORK ON CHIP; RESOURCE MANAGEMENT; RESOURCE MANAGEMENT PROCESS; RESOURCE MANAGEMENT TECHNIQUES; RUNTIMES; SYSTEM LEVELS; THROUGHPUT IMPROVEMENT;

ELECTRIC FAULT CURRENTS; EMBEDDED SYSTEMS; ENERGY UTILIZATION; MULTIPROCESSING SYSTEMS; NATURAL RESOURCES MANAGEMENT; RESOURCE ALLOCATION; VLSI CIRCUITS;

FAULT TOLERANCE;

EID: 79957552630     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. S. Shamshiri, et al., "A cost analysis framework for multi-core systems with spares," in Proc. Int. Test Conference, 2008.
2. T. Schonwald, et al., "Fully adaptive fault-tolerant routing algorithm for Network-on-Chip architecture," Proc. Digital System Design Architectures, Methods and Tools, 2007, pp. 527-534.
3. A. M. Pastrnak, et al., "Parallel implementation of arbitrary-shaped MPEG-4 decoder for multiprocessor Systems," in Proc. Visual Communication and Image Processing, Jan. 2006.
4. S. Bertozzi et al., "Supporting task migration in multi-processor systems- on-chip: a feasible study," in Proc. DATE, 2006, pp. 1-6.
5. T. T. Suen and J. S. Wong, "Efficient task migration algorithm for distributed systems," IEEE Trans. Parallel Distrib. Syst. vol. 3, 1992, pp. 488-499.
6. V. Lo, et al., "Non-contiguous processor allocation algorithms for mesh-connected multicomputers," IEEE Trans. on Parallel and Distributed Computing, 1997.
7. L. Huang, F. Yuan, and Q. Xu, "Lifetime reliability-aware task allocation and scheduling for MPSoC platforms," in Proc. DATE, 2009.
8. V. Nollet, T. Marescaux, and D. Verkest, "Operating-system controlled network on chip," in Proc. DAC, June 2004, pp. 256-259.
9. C-L Chou; R. Marculescu, "Contention-aware application mapping for Network-on-Chip communication architectures," in Proc. ICCD, Oct. 2008, pp.164-169.
10. S. Manolache, P. Eles, and Z. Peng, "Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC," in Proc. DAC, 2005, pp. 266-269.
11. M-L Li, et al., "Accurate microarchitecture-level fault modeling for studying hardware faults," Intl. Conf. on High Performance Computer Architecture, 2009, pp. 105-116.
12. S. Das, et al, "RazorII: In situ error detection and correction for PVT and SER tolerance," IEEE J. of Solid-State Circuits, pp.32-48, Jan. 2009.
13. T. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Proc. DAC, June 2002, pp. 524-529.
14. E. Carvalho, N. Calazans, and F. Moraes, "Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs," in Proc. IEEE/IFIP Workshop Rapid Syst. Prototyping, 2007, pp. 34-40.
15. http://lava.cs.virginia.edu/HotSpot/
16. http://www.sre.org/pubs/Mil-Hdbk-217F.pdf
17. http://www.sematech.org/docubase/document/3955axfr.pdf
18. Task graphs for free (TGFF v3.0) Keith Vallerio, 2003. [Online]. Available: http://ziyang.eecs.umich.edu/~dickrp/tgff/
19. M. F. Morris, "Kiviat graphs: conventions and figures of merit," SIGMETRICS Perform. Eval. Rev. 3, 3 (Oct. 1974), pp. 2-8.
20. http://src.alionscience.com/
21. http://ziyang.eecs.umich.edu/~dickrp/e3s/
22. P. Rantala, et al., "Agent-monitored fault-tolerant Network-on-Chips: Concept, hierarchy, and case study with FFT application," in DAC Workshop on Diagnostic Services in Network-on-Chips, April 2008.
23. M. A. Al Faruque, et al., "ADAM: run-time agent-based distributed application mapping for on-chip communication," in Proc DAC, 2008, pp. 760-765.