simulation points for SPEC CPU 2006

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 397-403

  Nair, Arun A ^a   John, Lizy K ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGGREGATE PERFORMANCE; BENCHMARK SUITES; DYNAMIC INSTRUCTIONS; INITIAL DESIGNS; LARGE GRAINS; SIMPOINT; STATISTICAL TECHNIQUES; TIME-CONSUMING PROCESS;

AGGREGATES;

EID: 62349141993     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751891     Document Type: Conference Paper

References (14)

1. Gove, D. 2007. CPU2006 working set size. SIGARCH Comput. Archit. News 35, 1 (Mar. 2007), 90-96.
2. Henning, J. L. 2007. SPEC CPU2006 memory footprint. SIGARCH Comput. Archit. News 35, 1 (Mar. 2007), 84-89
3. Sherwood, T., Perelman, E., Hamerly, G., and Calder, B. 2002. Automatically characterizing large scale program behavior. In Proceedings of the 10th international Conference on Architectural Support For Programming Languages and Operating Systems (San Jose, California, October 05 - 09, 2002). ASPLOSX. ACM, New York, NY, 45-57.
4. Burger, D.C. and Austin, T.M.. The SimpleScalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
5. Open Source Development Labs, Database Test 2, http://www.osdl.org/lab-activities/kernel-testing/osdl-database-test-suite/ osdl-dbt-2, 2007.
6. PIN home page: http://rogue.colorado.edu/Pin/
7. Standard Performance Evaluation Corporation (SPEC) website, http://www.spec.org/
8. Patil, H., Cohn, R., Charney, M., Kapoor, R., Sun, A., and Karunanidhi, A. 2004. Pinpointing Representative Portions of Large Intel ®Itanium® Programs with Dynamic Instrumentation. In Proceedings of the 37th Annual IEEE/ACM international Symposium on Microarchitecture (Portland, Oregon, December 04 - 08, 2004). International Symposium on Microarchitecture. IEEE Computer Society, Washington, DC, 81-92.
9. Luk, C., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., and Hazelwood, K. 2005. Pin: building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation (Chicago, IL, USA, June 12 - 15, 2005). PLDI '05. ACM, New York, NY, 190-200.
10. Perfmon2 home page http://perfmon2. sourceforge.net/
11. Sherwood, T., Perelman, E., and Calder, B. 2001. Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications. In Proceedings of the 2001 international Conference on Parallel Architectures and Compilation Techniques (September 08 - 12, 2001). PACT. IEEE Computer Society, Washington, DC, 3-14.
12. Conte, T. M., Hirsch, M. A., and Menezes, K. N. 1996. Reducing State Loss For Effective Trace Sampling of Superscalar Processors. In Proceedings of the 1996 international Conference on Computer Design, VLSI in Computers and Processors (October 07 - 09, 1996). ICCD. IEEE Computer Society, Washington, DC, 468-477.
13. Henning, J.L., SPEC CPU2000 Memory Footprint, http: //www.spec.org/ cpu2000/analysis/memory
14. Phansalkar, A., Joshi, A., and John, L. K. 2007. Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. In Proceedings of the 34th Annual international Symposium on Computer Architecture (San Diego, California, USA, June 09 - 13, 2007). ISCA '07