Neighborhood-aware data locality optimization for NoC-based multicores

Proceedings - International Symposium on Code Generation and Optimization, CGO 2011

Volumn , Issue , 2011, Pages 191-200

  Kandemir, Mahmut ^a   Zhang, Yuanrui ^a   Liu, Jun ^a   Yemliha, Taylan ^b  

^a The Center for Nanotechnology Education and Utilization   (United States)

^b Syracuse University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; COMPILER ALGORITHMS; CRITICAL ISSUES; DATA ACCESS; DATA LOCALITY; DATA LOCALITY OPTIMIZATION; DATA MOVEMENTS; DATA REUSE; MULTI CORE; MULTI-CORE SYSTEMS; MULTI-CORES; MULTI-THREADED APPLICATION; NETWORK ON CHIP; ON-CHIP CACHE; OVERALL EXECUTION;

EXPERIMENTS; NETWORK COMPONENTS; PROGRAM COMPILERS; SCHEDULING ALGORITHMS; SENSITIVITY ANALYSIS; VLSI CIRCUITS;

OPTIMIZATION;

EID: 79957447964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2011.5764687     Document Type: Conference Paper

References (39)

1. "Single-chip cloud computer," http://techresearch.intel.com/ articles/Tera-Scale/1826.htm.
2. "Teraflops research chip," http://techresearch.intel.com/ articles/Tera-Scale/1449.htm.
3. P. G. de Massas and F. Pétrot, "Comparison of memory write policies for NoC based multicore cache coherent systems," Proc. of DATE, 2008.
4. W. J. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," Proc. of DAC, 2001.
5. C. L. Chou and R. Marculescu, "Contention-aware application mapping for network-on-chip communication architectures," Proc. of ICCD, 2008.
6. Z. Chishti et al., "Distance associativity for high-performance energy-efficient non-uniform cache architectures," Proc. of Micro, 2003.
7. C. Kim et al., "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches," Proc. of ASPLOS, 2002.
8. B. M. Beckmann and D. A. Wood, "Managing wire delay in large chip-multiprocessor caches," Proc. of Micro, 2004.
9. J. F. Kurose and K. W. Ross, "Computer networking: A top-down approach featuring the internet," Addison Wesley, 2003.
10. W. Kelly et al., "The omega library interface guide," Technical Report, University of Maryland, 1995.
11. "Phoenix compiler infrastructure," Technical Report, Microsoft.
12. M. M. K. Martin et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Comput. Archit. News, 2005.
13. P. S. Magnusson et al., "Simics: A full system simulation platform," IEEE Computer, 2002.
14. N. Agarwal et al., "Garnet: A detailed interconnection network model inside a full-system simulation framework," Technical Report, Princeton University.
15. P. Shivakumar and N. P. Jouppi, "Cacti 3.0: An integrated cache timing, power, and area model," Technical Report, Western Research Laboratory.
16. C. Bienia et al., "The PARSEC benchmark suite: characterization and architectural implications," Technical Report, Princeton University, 2008.
17. V. Aslot et al., "SPEComp: A new benchmark suite for measuring parallel computer performance," 2001.
18. D. Weeratunga et al., "The NAS parallel benchmarks," NAS Technical Report, 1994.
19. M. E. Wolf et al., "Combining loop transformations considering caches and scheduling," Proc. of MICRO, 1996.
20. G. Chen et al., "Application mapping for chip multiprocessors," Proc. of DAC, 2008.
21. G. Ascia et al., "Multi-objective mapping for mesh-based noc architectures," Proc. of CODES+ISSS, 2004.
22. L. Jin et al., "A flexible data to L2 cache mapping approach for future multicore processors," Proc. of MSPC, 2006.
23. M. Kandemir et al., "Cache topology aware computation mapping for multicores," Proc. of PLDI, 2010.
24. T. Kempf et al., "A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platform," Proc. of DATE.
25. M. Ruggiero et al., "Communication-aware allocation and scheduling framework for stream-oriented multiprocessor systems-on-chip," Proc. of DATE, 2006.
26. V. Suhendra et al., "Integrated scratchpad memory optimization and task scheduling for MPSOC architectures," Proc. of CASES, 2006.
27. R. Pop and S. Kumar, "Mapping applications to NoC platforms with multithreaded processor resources." The NORCHIP Conference, 2005.
28. S. Chen et al., "Scheduling threads for constructive cache sharing on CMPs," Proc. of SPAA, 2007.
29. C. L. Chou and R. Marculescu, "User-aware dynamic task allocation in networks-on-chip," Proc. of DATE, 2008.
30. S. Sarkar and D. M. Tullsen, "Compiler techniques for reducing data cache miss rate on a multithreaded architecture," Proc. of HiPEAC, 2008.
31. M. Kandemir et al., "Optimizing shared cache behavior of chip multiprocessors," Proc. of MICRO, 2009.
32. E. P. Markatos and T. J. LeBlanc, "Using processor affinity in loop scheduling on shared-memory multiprocessors," Proc. of IPDPS, 1994.
33. M. Chu et al., "Data access partitioning for fine-grain parallelism on multicore architectures," Proc. of Micro, 2007.
34. A. Lu et al., "Data layout transformation for enhancing data locality on NUCA chip multiprocessors," Proc. of PACT, 2009.
35. E. Zhang et al., "Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?" Proc. of PPOPP, 2010.
36. Z. Chishti et al., "Optimizing replication, communication, and capacity allocation in CMPs," Proc. of ISCA, 2005.
37. C. Zhang et al., "A hierarchical model of data locality," Proc. of POPL, 2006.
38. R. Allen and K. Kennedy, Optimizing compilers for modern architectures: A dependence-based approach. Morgan Kaufmann.
39. M. Wolf, High-performance compilers for parallel computing. Addison-Wesley Publishing Company.