Data layout transformation for enhancing data locality on NUCA chip multiprocessors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 348-357

  Lu, Qingda ^a   Alias, Christophe ^b   Bondhugula, Uday ^a   Henretty, Thomas ^a   Krishnamoorthy, Sriram ^c   Ramanujam, J ^d   Rountev, Atanas ^a   Sadayappan, P ^a   Chen, Yongjian ^e   Ngai, Tin Fook ^e   Lin, Haibo ^f  

^a OHIO STATE UNIVERSITY   (United States)

^b UNIVERSITÉ DE LYON   (France)

^c PACIFIC NORTHWEST NATIONAL LABORATORY   (United States)

^d LOUISIANA STATE UNIVERSITY   (United States)

^e INTEL CORPORATION   (United States)

^f IBM CHINA RESEARCH LAB   (China)

Author keywords

Data layout optimization; NUCA cache; Polyhedral model

Indexed keywords

ADDRESS SPACE; ARRAY REFERENCES; CHIP MULTIPROCESSOR; COMPILE TIME; DATA ACCESS PATTERNS; DATA LAYOUT OPTIMIZATION; DATA LAYOUTS; DATA LOCALITY; DATA LOCALITY OPTIMIZATION; HOTSPOTS; L2 CACHE; LOCALIZABILITY; MULTI-PROCESSORS; NONLOCAL; POLYHEDRAL MODELS; PROGRAM TRANSFORMATION TECHNIQUES; SIMULATION-BASED; TILED ARCHITECTURE; TILED CMP;

MULTIPROCESSING SYSTEMS; OPTIMIZATION; PARALLEL ARCHITECTURES; SIMULATORS; SYSTEMS ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 70449628310     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.36     Document Type: Conference Paper

References (42)

1. R. N. Kalla, B. Sinharoy, and J. M. Tendler, "IBM POWER5 chip: A dual-core multithreaded processor," IEEE Micro, vol. 24, no. 2, pp. 40-47, 2004.
2. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-way multithreaded sparc processor," IEEE Micro, vol. 25, no. 2, pp. 21-29, 2005.
3. C. Kim, D. Burger, and S. W. Keckler, "An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches," in ASPLOS'02.
4. B. M. Beckmann and D. A. Wood, "Managing wire delay in large chip-multiprocessor caches," in MICRO'04.
5. B. S. Andersen, F. G. Gustavson, A. Karaivanov, M. Marinova, J. Waniewski, and P. Y. Yalamov, "Lawra: Linear algebra with recursive algorithms," in PARA '00. London, UK: Springer-Verlag, 2001, pp. 38-51.
6. P. Feautrier, "Some efficient solutions to the affine scheduling problem: I. one-dimensional time," IJPP, vol. 21, no. 5, pp. 313-348, 1992.
7. W. Pugh and D. Wonnacott, "Constraint-based array dependence analysis," ACM Trans. Program. Lang. Syst., vol. 20, no. 3, pp. 635-678, 1998.
8. W. Kelly and W. Plugh, "Minimizing communication while preserving parallelism," in ICS '96. New York, NY, USA: ACM, 1996, pp. 52-60.
9. F. Quilleré, S. V. Rajopadhye, and D. Wilde, "Generation of efficient nested loops from polyhedra," Intl. J. of Parallel Programming, vol. 28, no. 5, pp. 469-498, 2000.
10. "CLooG: The Chunky Loop Generator," http://www.cloog.org.
11. L.-N. Pouchet, C. Bastoul, J. Cavazos, and A. Cohen, "Iterative optimization in the polyhedral model: Part II, multidimensional time," in PLDI'08, Tucson, Arizona, June 2008.
12. U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, "A practical automatic polyhedral parallelizer and locality optimizer," in PLDI '08. New York, NY, USA: ACM, 2008, pp. 101-113.
13. "GCC: GCC, the GNU Compiler Collection, Version 4.3.2, " http://gcc.gnu.org.
14. M. Griebl, Automatic Parallelization of Loop Programs for Distributed Memory Architectures. FMI, University of Passau, 2004, habilitation Thesis. [Online]. Available: http://www.uni-passau.de/~griebl/habilitation.html
15. J. M. Anderson, S. P. Amarasinghe, and M. S. Lam, "Data and computation transformations for multiprocessors," in PPOPP'95.
16. G. Rivera and C.-W. Tseng, "Data transformations for eliminating conflict misses," in PLDI'98.
17. S. Amarasinghe, Paralelizing Compiler Techniques Based on Linear Inequalities. Stanford University, 1997, phD Dissertation. [Online]. Available: http://suif.stanford.edu/papers/amarasinghe97.ps
18. Virtutech AB, "Simics full system simulator," http://www.simics.com.
19. M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu, A. Alameldeen, K. Moore, M. Hill, and D. Wood, "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Comput. Archit. News, vol. 33, no. 4, pp. 92-99, 2005.
20. M. R. Marty and M. D. Hill, "Virtual hierarchies to support server consolidation," in ISCA'07.
21. D. Tarditi, S. Puri, and J. Oglesby, "Accelerator: using data parallelism to program gpus for general-purpose uses," in ASPLOS'06.
22. B. L. Chamberlain, S.-E. Choi, E. C. Lewis, C. Lin, L. Snyder, and W. D. Weathersby, "ZPL: A machine independent programming language for parallel computers," IEEE TSE, vol. 26, no. 3, pp. 197-211, 2000.
23. "LooPo - Loop parallelization in the polytope model," http://www.fmi.uni-passau.de/loopo.
24. N. Magen, A. Kolodny, U. Weiser, and N. Shamir, "Interconnect-power dissipation in a microprocessor," in SLIP'04, 2004.
25. L. Shang, L.-S. Peh, and N. K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in HPCA'03.
26. G. Chen, F. Li, M. Kandemir, and M. J. Irwin, "Reducing NoC energy consumption through compiler-directed channel voltage scaling," in PLDI'06.
27. F. Li, G. Chen, M. Kandemir, and I. Kolcu, "Profile-driven energy reduction in network-on-chips," in PLDI'07.
28. D. S. Nikolopoulos, T. S. Papatheodorou, C. D. Polychronopoulos, J. Labarta, and E. Ayguadé, "A case for userlevel dynamic page migration," in ICS'00.
29. R. Chandra, S. Devine, B. Verghese, A. Gupta, and M. Rosenblum, "Scheduling and page migration for multiprocessor compute servers," in ASPLOS'94.
30. S. Leung and J. Zahorjan, "Optimizing data locality by array restructuring," Dept. Computer Science, University of Washington, Seattle, WA, Tech. Rep. TR-95-09-01, 1995.
31. M. F. P. O'Boyle and P. M. W. Knijnenburg, "Non-singular data transformations: definition, validity, applications," in CPC'96.
32. M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, and J. Ramanujam, "A linear algebra framework for automatic determination of optimal data layouts," IEEE TPDS, vol. 10, no. 2, pp. 115-135, 1999.
33. M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and E. Ayguade, "Static and dynamic locality optimizations using integer linear programming," IEEE TPDS, vol. 12, no. 9, pp. 922-941, 2001.
34. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "Improving locality using loop and data transformations in an integrated framework," in MICRO'98.
35. S. Chatterjee, J. R. Gilbert, R. Schreiber, and S.-H. Teng, "Automatic array alignment in data-parallel programs," in POPL'93. New York, NY, USA: ACM Press, 1993, pp. 16-28.
36. R. Barua, W. Lee, S. Amarasinghe, and A. Agarwal, "Maps: a compiler-managed memory system for raw machines," in ISCA'99.
37. B. So, M. W. Hall, and H. E. Ziegler, "Custom data layout for memory parallelism," in CGO'04.
38. S. Chatterjee, A. R. Lebeck, P. K. Patnala, and M. Thottethodi, "Recursive array layouts and fast parallel matrix multiplication," in SPAA'99.
39. S. Chatterjee, V. V. Jain, A. R. Lebeck, S. Mundhra, and M. Thottethodi, "Nonlinear array layouts for hierarchical memory systems," in ICS'99.
40. S. Chatterjee and S. Sen, "Cache-efficient matrix transposition," in HPCA'00.
41. A. W. Lim and M. S. Lam, "Maximizing parallelism and minimizing synchronization with affine partitions," Parallel Computing, vol. 24, no. 3-4, pp. 445-475, 1998.
42. A. W. Lim, G. I. Cheong, and M. S. Lam, "An affine partitioning algorithm to maximize parallelism and minimize communication," in ICS'99, 1999, pp. 228-237.