Optimizing shared cache behavior of chip multiprocessors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 505-516

  Kandemir, Mahmut ^a   Muralidhara, Sai Prashanth ^a   Narayanan, Sri Hari Krishna ^a,c   Zhang, Yuanrui ^a   Ozturk, Ozcan ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b BILKENT UNIVERSITY   (Turkey)

^c ARGONNE NATIONAL LABORATORY   (United States)

Author keywords

Algorithm; B.3.2 memory structures : design styles cache memories; D.3.4 programming languages : processors compilers; Design; Experimentation; Performance

Indexed keywords

D.3.4 [PROGRAMMING LANGUAGES]: PROCESSORS - COMPILERS; DESIGN STYLES; EXPERIMENTATION; MEMORY STRUCTURE; PERFORMANCE; PROGRAMMING LANGUAGE;

COMPUTER SOFTWARE; DESIGN; EXPERIMENTS; LINGUISTICS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PROGRAM COMPILERS;

CACHE MEMORY;

EID: 76749137634     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669176     Document Type: Conference Paper

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