Achieving stable through-silicon via (TSV) capacitance with oxide fixed charge

IEEE Electron Device Letters

Volumn 32, Issue 5, 2011, Pages 668-670

  Zhang, L ^a,b   Li, H Y ^a   Gao, S ^a   Tan, C S ^b,c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c RESEARCH TECHNO PLAZA   (Singapore)

Author keywords

Capacitance; oxide fixed charge; through silicon via (TSV)

Indexed keywords

3-D INTEGRATION; C-V CURVE; DIELECTRIC LINERS; HIGH ASPECT RATIO; LOW LATENCY; OPERATING VOLTAGE; OPERATING VOLTAGE RANGE; OXIDE FIXED CHARGE; PARASITIC CAPACITANCE; SIGNAL TRANSMISSION; THROUGH-SILICON VIA (TSV);

ASPECT RATIO;

CAPACITANCE;

EID: 79955536912     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2111351     Document Type: Article

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