Through-silicon-via capacitance reduction technique to benefit 3-D IC performance

IEEE Electron Device Letters

Volumn 31, Issue 6, 2010, Pages 549-551

  Katti, Guruprasad ^a,b   Stucchi, Michele ^a   Van Olmen, Jan ^a   De Meyer, Kristin ^a,b   Dehaene, Wim ^a,b  

^a IMEC   (Belgium)

^b Katholieke Universiteit Leuven   (Belgium)

Author keywords

3 D integrated circuits; Through silicon via (TSV); TSV capacitance

Indexed keywords

3-D INTEGRATED CIRCUIT; 3-D INTEGRATED CIRCUITS; C-V CHARACTERISTIC; CAPACITANCE REDUCTION; CIRCUIT OPERATION; KEY COMPONENT; MANUFACTURING PROCESS; OPERATING VOLTAGE; SILICON SUBSTRATES; THROUGH-SILICON VIA (TSV); THROUGH-SILICON-VIA;

ELECTRONICS PACKAGING; INTEGRATED CIRCUITS; THREE DIMENSIONAL;

CAPACITANCE;

EID: 77953026096     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2046712     Document Type: Article

References (11)

1. A. Rahman and R. Reif, "System-level performance evaluation of three-dimensional integrated circuits," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.8, no.6, pp. 671-678, Dec. 2000.
2. A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, "Three-dimensional integrated circuits," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491-506, Jul.-Sep. 2006.
3. H. Kurino, K. W. Lee, T. Nakamura, K. Sakuma, K. T. Park, N. Miyakawa, H. Shimazutsu, K. Y. Kim, K. Inamura, and M. Koyanagi, "Intelligent image sensor chip with three dimensional structure," in IEDM Tech. Dig., 1999, p. 879.
4. G. Katti, A. Mercha, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Stucchi, M. Rakowski, I. Debusschere, P. Soussan, W. Dehaene, K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, and B. Swinnen, "3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding," in IEDM Tech. Dig., 2009, pp. 357-360.
5. H. Kikuchi, Y. Yamada, A. Ali, J. Liang, T. Fukushima, T. Tanaka, and M. Koyanagi, "Tungsten through-silicon via technology for three-dimensional LSIs," Jpn. J. Appl. Phys., vol.47, no.4, pp. 2801-2806, 2008.
6. J. Walker, "TSV\First or Last, Fact or Fiction, Now or Future?" Gartner Dataquest 2008.
7. E. M. Chow, V. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F. Quate, and T. W. Kenny, "Process compatible polysilicon-based electrical through wafer interconnects in silicon substrates," J. Micro-electromech. Syst., vol.11, no.6, pp. 631-640, Dec. 2002.
8. G. Katti, M. Stucchi, K. De Mayer, and W. Dehaene, "Electrical modeling & characterization of through silicon via (TSV) for 3D ICs," IEEE Trans. Electron Devices, vol.57, no.1, pp. 256-262, Jan. 2010.
9. H. Saito, Y. Hagihara, and H. Ikeda, "Semiconductor chip and semiconductor device," U.S. 0 145 301, Jul. 6, 2006.
10. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
11. G. S. Sandhu and R. Iyer, "Method to reduce fixed charge in CVD ozone deposited films," U.S. Patent Application 20 060 029 736, Jul. 27, 2005. [Online]. Available: http://www.edswafer.net/300MMProducts.htm