Process integration considerations for 300 mm TSV manufacturing

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 4, 2009, Pages 524-528

  Ramaswami, Sesh ^a   Dukovic, John ^a   Eaton, Brad ^a   Pamarthy, Sharma ^a   Bhatnagar, Ajay ^a   Cao, Zhitao ^a   Sapre, Kedar ^a   Wang, Yuchun ^a   Kumar, Ajay ^a  

^a NONE

Author keywords

Chemical vapor deposition (CVD); Chemical mechanical planarization (CMP); Electrochemically deposition (ECD); Etch; Etching; Physical vapor deposition (PVD); Through silicon via (TSV)

Indexed keywords

CHEMICAL-MECHANICAL PLANARIZATION; CMOS IMAGE SENSOR; CUSTOMER VALUES; ELECTROCHEMICALLY DEPOSITION; ELECTROCHEMICALLY DEPOSITION (ECD); ETCH; FORM FACTORS; HIGH-VOLUME PRODUCTION; MANUFACTURABILITY; MEMORY SEGMENTS; PROCESS INTEGRATION; VALUE CHAINS;

APPROXIMATION THEORY; DEPOSITION; ELECTROCHEMICAL SENSORS; ELECTROCHROMIC DEVICES; ETCHING; IMAGE SENSORS; NANOTECHNOLOGY; PHYSICAL VAPOR DEPOSITION; REDUCTION;

CHEMICAL VAPOR DEPOSITION;

EID: 72649096507     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2009.2034317     Document Type: Conference Paper

References (3)

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3. P. S. Andry, C. Tsang, E. Sprogis, C. Patel, S. L. Wright, and B. C. Webb, "A CMOS-compatible process for fabricating electrical through-vias in silicon," in Proc. 56th Electron. Compon. Technol. Conf., May 30-Jun. 2, 2006, pp. 831-837.