Double SiGe:C diffusion barrier channel 40nm CMOS with improved short-channel performances

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 437-440

  Ducroquet, F ^a,b   Ernst, T ^a   Hartmann, J M ^a   Weber, O ^a,b   Andrieu, F ^a   Holliger, P ^a   Laugier, F ^a   Rivallin, P ^a   Guegan G ^a   Lafond, D ^a   Laviron, C ^a   Carron, V ^a   Brevard L ^a   Tabone, C ^a   Bouchu, D ^a   Toffoli, A ^a   Cluzel, J ^a   Deleonibus, S ^a  

^a CEA GRENOBLE   (France)

^b INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; DIFFUSION; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DOPING; CMOS INTEGRATED CIRCUITS;

BORON DIFFUSION; CHANNEL EFFECTS; DIFFUSION BARRIERS; GATE LENGTH;

CMOS INTEGRATED CIRCUITS; DIFFUSION BARRIERS;

% REDUCTIONS; BENEFICIAL EFFECTS; BORON DIFFUSIONS; CMOS DEVICES; DOPING PROFILES; DOWN-SCALING; GATE-LENGTH; JUNCTION DEPTH; SHORT-CHANNEL EFFECT; SHORT-CHANNEL PERFORMANCE;

EID: 21644456208     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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7. xMOS device", IEDM Tech Dig., p. 379, 2002