MOSFET design for forward body biasing scheme

IEEE Electron Device Letters

Volumn 27, Issue 5, 2006, Pages 387-389

  Hokazono, Akira ^a   Balasubramanian, Sriram ^a   Ishimaru, Kazunari ^b   Ishiuchi, Hidemi ^b   Liu, Tsu Jae King ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

Body bias; Forward bias; MOSFET; Reverse bias; Substrate bias; Work function

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MOSFET DEVICES; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DOPING;

BODY BIAS; CHANNEL DOPING PROFILE; FORWARD BIAS; GATE WORK FUNCTION; REVERSE BIAS; SUBSTRATE BIAS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 33646267440     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.873382     Document Type: Article

References (7)

1. H. Koura, M. Takamiya, and T. Hiramoto, "Optimum conditions of body effect factor and substrate bias in various threshold voltage MOSFETs," Jpn. J. Appl. Phys., vol. 39, no. 413, pp. 2312-2317, Apr. 2000.
2. S.-F. Huang, C. Wann, Y.-S. Huang, C.-Y. Lin, T. Schafbauer, S.-M. Cheng, Y.-C. Cheng, K.-C. Juan, D. Vietzke, M. Eller, C. Lin, Q. Ye, N. Rovedo, S. Biesemans, P. Nguyen, R. Dennard, and B. Chen, "Scalability and biasing strategy for CMOS with active well bias," in VLSI Symp. Tech. Dig., 2001, pp. 107-108.
3. S. Borkar, "Circuit techniques for subthreshold leakage avoidance, control, and tolerance," in IEDM Tech. Dig., 2004, pp. 421-424.
4. DD and back-bias control with reliability consideration for back-bias mode," in VLSI Symp. Tech. Dig., 2004, pp. 88-89.
5. N. Kimizuka, Y. Yasuda, T. Iwamoto, I. Yamamoto, K. Tanaka, Y. Akiyama, and K. Imai, "Ultralow standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme," in VLSI Symp. Tech. Dig., 2005, pp. 218-219.
6. C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, "Hot-electron-induced MOSFET degradation - Model, monitor, and improvement," IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 375-385, Feb. 1985.
7. F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, "Dynamic threshold-voltage MOSFET (DTMOS) for ultralow voltage VLSI," IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 414-422, Mar. 1997.