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Volumn 50, Issue 4 PART 2, 2011, Pages

Multi-gate fin field-effect transistors junctions optimization by conventional ion implantation for (Sub-)22nm technology nodes circuit applications

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; CIRCUIT APPLICATION; CONDUCTION CHANNEL; CRITICAL DIMENSION CONTROL; CRITICAL PARAMETER; CYCLE TIME; DEFECT-FREE GROWTH; DEVICE PERFORMANCE; FIN FIELD-EFFECT TRANSISTORS; FINFETS; GATE FIELD; LOW ENERGIES; RAISED SOURCE/DRAIN; REDUCED COST; SHADOWING EFFECTS; SILICON FINS; STATIC NOISE MARGIN; STATIC RANDOM ACCESS MEMORY; TECHNOLOGY NODES;

EID: 79955403676     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.50.04DC16     Document Type: Article
Times cited : (12)

References (20)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.