Power aware variable partitioning and instruction scheduling for multiple memory banks

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 312-317

  Wang, Zhong ^a   Hu, Xiaobo Sharon ^a  

^a University of Notre Dame   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; FILE ORGANIZATION; GRAPH THEORY; ITERATIVE METHODS; MATHEMATICAL MODELS; PROGRAM COMPILERS; SCHEDULING; DESIGN; EXHIBITIONS;

ADDRESS GENERATION UNITS (AGU); INSTRUCTION SCHEDULING; MULTIPLE MEMORY BANKS; PROGRAM EXECUTION;

DATA STORAGE EQUIPMENT; PROGRAM COMPILERS;

COMPILER DESIGN; DSP PROCESSOR; IMPROVE PERFORMANCE; INSTRUCTION SCHEDULING; PERFORMANCE CONSTRAINTS; POWER DEMANDS; REGISTER FILES; VARIABLE PARTITIONS;

EID: 3042723370     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. 128/144-mbit direct rdram data sheet, May 1999. Rambus Inc.
2. 1mb syncburst sram data sheet, Sept. 1999. Micron Technology Inc.
3. S. A and T. S. Malik. Simultaneous reference allocation in code generation for dual data memory bank asips. ACM TO-DAES, 5(2), 2000.
4. G. Ausiello, P. Crescenzi, G. Gambosi, V. Kann, A. Marchetti-Spaccamela, and M. Protasi. Complexity and Approximation. Springer Verlag, 1999. ISBN 3-540-65431-3.
5. L. Benini, A. Macii, and M. Poncino. A recursive algorithm for low-power memory partitioning. In International Symposium on Low power Electronics and Design, Aug 2000.
6. F. Catthoor, S. Wuytack, E. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom Memory Management Methodology - Exploration of Memory Organization for Embedded Multimedia System. Kluwer Academic, 1998.
7. J. Cho, Y. Paek, and D. Whalley. Efficient register and memory assignment for non-orthogonal architectures via graph coloring and mst algorithms. In ACM Joint Conference LCTES-SCOPES, pages 130-138, Berlin, Germany, Jun 2002.
8. V. Delaluz, N. V. M. Kandemir, A. Sivasubramaniam, and M. J. Irwin. Hardware and software techniques for controlling dram power modes. IEEE Transactions on Computers, 50(11), Nov 2001.
9. V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Scheduling techniques for embedded systems: Scheduler-based dram energy management. In 39th conference on Design automation, June 2002.
10. R. Leupers and D. Kotte. Variable partitioning for dual memory bank dsps. In Proceeding of ICASSP, 2001.
11. M. Lorenz, D. Kottmann, S. Bashfrod, R. Leupers, and P. Marwedel. Optimized address assignment for dsps with simd memory accesses. In Asia South Pacific Design Automation Conference (ASP-DAC), pages 415-420, Yokohama, Japan, Jan 2001.
12. Y. H. Lu, L. Benini, and G. D. Micheli. Low-power task scheduling for multiple devices. In 8th international workshop on Hardware/software codesign, May 2000.
13. V. D. L. Luz, M. Kandemir, and I. Kolcu. Memory management and address optimization in embedded systems: Automatic data migration for reducing energy consumption in multi-bank memory systems. In 39th conference on Design automation, Jun 2002.
14. R. Prim. Shortest connection networks and some generalizations. Bell Systems Technical Journal, 36(6), 1957.
15. M. Saghir, P. Chow, and C. Lee. Exploiting dual data-memory banks in digital signal processors. In 7th International Conference on Architecture Support for Programming Language and Operating Systems, pages 234-243, 1996.
16. S. Wuytack, F. Catthoor, G. D. Jong, and H. D. Man. Minimizing the required memory bandwidth in vlsi system realizations. IEEE Trans. on VLSI Systems, 7(4), DEC 1999.
17. T. Zeithofer and B. Wess. Integrated scheduling and register assignment for vliw-dsp architectures. In 14th Annual IEEE International ASIC/SOC Conference, pages 339-343, 2001.
18. Q. Zhuge, B. Xiao, and E. H.-M. Sha. Exploring variable partitioning in dual data-memory bank processors. In Proc. of the 34th International Symposium on Micro-architecture (MICRO-34), the 3rd Workshop on Media and Streaming Processors (MSP-3 Workshop), pages 42-55, Dec 2001.
19. V. Zivoljnovic, J. Velarde, C. Schager, and H. Meyr. Dspstone - a dsp oriented benchmarking methodology. In Proceedings of International Conference on Signal Processing Applications and Technology, 1994.