A compiler approach to managing storage and memory bandwidth in configurable architectures

ACM Transactions on Design Automation of Electronic Systems

Volumn 13, Issue 4, 2008, Pages

  Baradaran, Nastaran ^a,c   Diniz, Pedro C ^b,d  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b INSTITUTO SUPERIOR TÉCNICO   (Portugal)

^c CISCO SYSTEMS   (United States)

^d UNIVERSITY OF LISBON   (Portugal)

Author keywords

Compiler analysis; Configurable architectures; High level hardware synthesis; Storage allocation and management

Indexed keywords

COMPILER ANALYSIS; CONFIGURABLE ARCHITECTURES; HIGH-LEVEL HARDWARE SYNTHESIS; STORAGE ALLOCATION AND MANAGEMENT;

BOOLEAN FUNCTIONS; CONFORMAL MAPPING; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM COMPILERS; TELECOMMUNICATION SYSTEMS; WIRELESS TELECOMMUNICATION SYSTEMS;

DATA STORAGE EQUIPMENT;

EID: 53849105813     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1391962.1391969     Document Type: Article

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