Memory access scheduling and binding considering energy minimization in multi-bank memory systems

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 81-86

  Lyuh, Chun Gi ^a   Kim, Taewhan ^b  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

Binding; Low energy design; Scheduling

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; DATA STORAGE EQUIPMENT; ENERGY UTILIZATION; HEURISTIC PROGRAMMING; KALMAN FILTERING; POTENTIAL ENERGY; PROBLEM SOLVING; PROGRAM PROCESSORS; SCHEDULING; STATIC RANDOM ACCESS STORAGE;

BINDING; ENERGY MINIMIZATION; LOW ENERGY DESIGN; MEMORY SYSTEMS;

EMBEDDED SYSTEMS;

EID: 4444379668     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996596     Document Type: Conference Paper

References (13)

1. A. Sudarsanam and S. Malik, "Simultaneous Reference Allocation in Code Generation for Dual Data Memory Bank ASIPs," ACM TODAES, Vol. 5, 2000.
2. J. Cho, Y. Paek, and D. Whalley, "Effi cient Register and Memory Assignment for Non-orthogonal Architecture Via Graph Coloring and MST Algorithms," ACM Joint Conference LCTES-SCOPES, 2002.
3. V. De La Luz, M. Kandemir, and I. Kolcu, "Automatic Data Migration for Reducing Energy Consumption in Multi-Bank Memory Systems," DAC, 2002.
4. L. Benini, A. Macii, and M. Poncino, "A Recursive Algorithm for Low-Power Memory Partitioning," ISLPED, 2000.
5. L. Benini, L. Macchiarulo, A. Macii, and M. Poncino, "Layout-driven memory synthesis for embedded systems-on-chip," IEEE TVLSI, Vol. 10, 2002.
6. Y-H. Lu, L. Benini, and G. De Micheli, "Low Power Task Scheduling for Multiple Devices," International Workshop on Hardware/Software Codesign, 2000.
7. V. De La Luz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, "Scheduler-Based DRAM Energy Management," DAC, 2002.
8. V. De La Luz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam and M. J. Irwin, "Hardware and Software Techniques for Controlling DRAM Power Modes," IEEE TC, Vol. 50, 2001.
9. 128/144-MBit Direct RDRAM Data Sheet, Rambus Inc., May 1999.
10. A. Aho, J. Hopcroft, and J. Ullman, The Design and Analysis of Computer Algorithms, Addison-Wesley, 1974.
11. P. R. Panda and N. D. Dutt, "High-Level Synthesis Design Repository", Proc. of ISSS (http://www.ics.uci.edu/dutt), 1995.
12. W. H. Press, et al. (Editors), Numerical Recipes in C: The Art of Scientific Computing, Cambridge University Press, 1993.
13. V. Zivojnovic, J. Velarde, and C. Schlager, "Dspstone: A DSP-oriented Benchmarking Methodology," International Conference on Signal Processing Applications and Technology, 1994.