MemScale: Active low-power modes for main memory

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2011, Pages 225-238

  Deng, Qingyuan ^a   Meisner, David ^b   Ramos, Luiz ^a   Wenisch, Thomas F ^b   Bianchini, Ricardo ^a  

^a RUTGERS UNIVERSITY   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Dynamic voltage and frequency scaling; Energy conservation; Memory subsystem

Indexed keywords

CONSERVE ENERGY; DRAM DEVICES; DYNAMIC FREQUENCY SCALING; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ENERGY CONSUMPTION; HARDWARE COST; LOW POWER; LOW-POWER MODE; MAIN MEMORY; MEMORY BANDWIDTHS; MEMORY CHANNELS; MEMORY CONTROLLER; MEMORY SUBSYSTEM; MEMORY SUBSYSTEMS; OPERATING SYSTEMS; PERFORMANCE DEGRADATION; POTENTIAL BENEFITS;

DYNAMIC RANDOM ACCESS STORAGE; ENERGY UTILIZATION; QUERY LANGUAGES;

ENERGY CONSERVATION;

EID: 79953071808     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1950365.1950392     Document Type: Conference Paper

References (45)

1. J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future scaling of processor-memory interfaces. SC '09 - Super Computing, 2009.
2. I. Akyildiz. On the exact and approximate throughput analysis of closed queuing networks with blocking. IEEE Transactions on Software Engineering, 14(1):62-70, 1988. (Pubitemid 18595931)
3. AMD. ACP - The Truth About Power Consumption Starts Here, 2009. http://www.amd.com/us/Documents/43761C-ACP-WP-EE.pdf.
4. S. Balsamo, V. D. N. Persone, and R. Onvural. Analysis of Queuing Networks with Blocking. 2001.
5. L. A. Barroso and U. Hölzle. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines. Synthesis Lectures on Computer Architecture, Jan. 2009.
6. L. A. Barroso and U. Hölzle. The Case for Energy-Proportional Computing. IEEE Computer, 40(12):33-37, December 2007.
7. N. Binkert, R. Dreslinski, L. Hsu, K. Lim, a.G. Saidi, and S. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4):52-60, July 2006. (Pubitemid 46504889)
8. R. Crisp. Direct Rambus Technology: The New Main Memory Standard. IEEE Micro, 1997.
9. R. Das, O. Mutlu, T. Moscibroda, and C. R. Das. Aérgia : Exploiting Packet Latency Slack in On-Chip Networks. ISCA '10: International Symposium on Computer Architecture, 2010.
10. V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Transactions on Computers, 50(11), 2001.
11. B. Diniz, D. Guedes, W. M. Jr, and R. Bianchini. Limiting the Power Consumption of Main Memory. ISCA '07: International Symposium on Computer Architecture, 2007.
12. EPA. Report to Congress on Server and Data Center Energy Efficiency Public Law 109-431, 2007.
13. X. Fan, C. Ellis, and A. Lebeck. Memory Controller Policies for DRAM Power Management. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.
14. W. Felter, K. Rajamani, T. Keller, and C. Rusu. A Performance- Conserving Approach for Reducing Peak Power Consumption in Server Systems. ICS '05: International Conference on Supercomputing, 2005.
15. Google. Going Green at Google, 2010.
16. E. Gorbatov, 2010. Personal communication.
17. M. S. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. HPCA '08: High Performance Computer Architecture, 2008.
18. H. Hanson and K. Rajamani. What Computer Architects Need to Know About Memory Throttling. WEED '10: Workshop on Energy-Efficient Design, 2010.
19. S. Herbert and D. Marculescu. Analysis of Dynamic Voltage/ Frequency Scaling in Chip-Multiprocessors. ISLPED '07: International Symposium on Low Power Electronics and Design, 2007.
20. H. Huang, P. Pillai, and K. G. Shin. Design and Implementation of Power-Aware Virtual Memory. In Proceedings of the USENIX Annual Technical Conference, June 2003.
21. Intel. Intel Xeon Processor 5600 Series, 2010.
22. B. Jacob, S.W. Ng, and D. T.Wang. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers, 2007.
23. JEDEC. DDR3 SDRAM Standard, 2009.
24. A. R. Lebeck, X. Fan, H. Zeng, and C. Ellis. Power Aware Page Allocation. ASPLOS '00: Architectural Support for Programming Languages and Operating Systems, 2000.
25. C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller. Energy Management for Commercial Servers. IEEE Computer, 36(12), December 2003.
26. D. Levinthal. Performance Analysis Guide for Intel Core i7 Processor and Intel Xeon 5500 processors, 2009.
27. X. Li, Z. Li, F. M. David, P. Zhou, Y. Zhou, S. V. Adve, and S. Kumar. Performance-directed energy management for main memory and disks. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, October 2004.
28. K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. K. Reinhardt, and T. F. Wenisch. Disaggregated Memory for Expansion and Sharing in Blade Servers. ISCA '09: International Symposium on Computer Architecture, 2009.
29. J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Thermal Modeling and Management of DRAM Memory Systems. ISCA '07: International Symposium on Computer Architecture, 2007.
30. J. Lin, H. Zheng, Z. Zhu, E. Gorbatov, H. David, and Z. Zhang. Software Thermal Management of DRAM Memory for Multicore Systems. SIGMETRICS, pages 337-348, 2008.
31. D. Meisner, B. T. Gold, and T. F. Wenisch. PowerNap: Eliminating Server Idle Power. ASPLOS '09: Architectural Support for Programming Languages and Operating Systems, Feb. 2009.
32. Micron. 1Gb: x4, x8, x16 DDR3 SDRAM, 2006.
33. Micron. Calculating Memory System Power for DDR3, July 2007.
34. A. Miyoshi, C. Lefurgy, E. V. Hensbergen, R. Rajamony, and R. Rajkumar. Critical Power Slope : Understanding the Runtime Effects of Frequency Scaling. ICS '02: International Conference on Supercomputing, 2002.
35. J. Moore, J. S. Chase, and P. Ranganathan. Weatherman: Automated, Online and Predictive Thermal Mapping and Management for Data Centers. ICAC '06: International Conference on Autonomic Computing, 2006.
36. V. Pandey, W. Jiang, Y. Zhou, and R. Bianchini. DMA-Aware Memory Energy Management. HPCA '06: High-Performance Computer Architecture, 2006.
37. S. Pelley, D. Meisner, P. Zandevakili, T. F. Wenisch, and J. Underwood. Power Routing : Dynamic Power Provisioning in the Data Center. ASPLOS '10: Architectural Support for Programming Languages and Operating Systems, 2010.
38. E. Perelman, G. Hamerly, M. V. Biesbrouck, T. Sherwood, and B. Calder. Using SimPoint for Accurate and Efficient Simulation Erez Perelman. SIGMETRICS, 2003.
39. L. Ramos and R. Bianchini. C-Oracle: Predictive thermal management for data centers. HPCA '08: High Performance Computer Architecture, Feb. 2008.
40. K. Sudan, N. Chatterjee, D. Nellans, M. Awasthi, Rajeev Balasubramonian, and A. Davis. Micro-Pages : Increasing DRAM Efficiency with Locality-Aware Data Placement. ASPLOS '10: Architectural Support for Programming Languages and Operating Systems, 2010.
41. N. Tolia, Z. Wang, M. Marwah, C. Bash, P. Ranganathan, and X. Zhu. Delivering Energy Proportionality with Non Energy-Proportional Systems Optimizing the Ensemble. HotPower, 2008.
42. D. Tsirogiannis, S. Harizopoulos, and M. A. Shah. Analyzing the energy efficiency of a database server. SIGMOD, 2010.
43. A. N. Udipi, N. Muralimanohar, N. Chatterjee, Rajeev Balasubramonian, A. Davis, and N. P. Jouppi. Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores. ISCA '10: International Symposium on Computer Architecture, 2010.
44. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Minirank: Adaptive DRAM architecture for improving memory power efficiency. MICRO '08: Symposium on Microarchitecture, Nov. 2008.
45. H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. Decoupled DIMM : Building High-Bandwidth Memory System Using Low-Speed DRAM Devices. ISCA '09: International Symposium on Computer Architecture, 2009.