Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 165-170

  Shin, Tae Ho ^a   Oh, Hyunok ^b   Ha, Soonhoi ^a  

^a Seoul National University   (South Korea)

^b Hanyang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER REQUIREMENTS; BUFFER SIZES; DYNAMIC SCHEDULING; KEY ISSUES; NP-HARD; PARALLEL EXECUTIONS; STATIC MAPPING; STATIC SCHEDULING; SYNCHRONOUS DATA FLOW GRAPHS; THROUGHPUT CONSTRAINTS; THROUGHPUT PERFORMANCE;

COMPUTER AIDED DESIGN; RESPONSE TIME (COMPUTER SYSTEMS); THROUGHPUT;

DATA FLOW ANALYSIS;

EID: 79952923866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722178     Document Type: Conference Paper

References (19)

1. th International Conference on Compiler Construction, Grenoble (France), Apr. 2002
2. E. A. Lee and D. G. Messerschmitt, "Static scheduling of synchronous data flow programs for digital signal processing," IEEE Trans. On Comp., vol. 36, no. 1, pp. 24-35, 1987.
3. G. Bilsen, M. Engles, R. Lauwereins, and J.A. Peperstraete, "Cyclo-Static Dataflow," IEEE Trans. Signal Processing, 44(2), pp. 397-408, 1996.
4. S. Bhattacharyya, E. Lee, and P. Murthy, Software Synthesis from Dataflow Graphs, Kluwer, 1996.
5. th Design Automation Conf., June, 1998.
6. P. D. Hoang and J. M. Rabaey, "Scheduling of DSP Programs Onto Multiprocessors for Maximum Throughput," IEEE Trans. On Signal Processing, pp. 2225-2235, June 1993.
7. S. Bakshi and D. D. Gajski, "Partitioning and pipelining for performance-constrained hardware/software systems," IEEE Transactions on VLSI Systems, vol. 7, no. 4, pp. 419-432, Dec. 1999.
8. K. S. Chatha and R. Vemuri, "hardware-software partitioning and pipelined scheduling of transformative applications," IEEE Trans. On VLSI, 10(30), 2002.
9. L. Benini, D. Bertozzi, A. Guerri, and M. Milano, "Allocation and scheduling for MPSoCs via decomposition and no-good generation," in Proc. of International Joint Conferences on Artificial Intelligence, 2005.
10. V. Suhendra, C. Raghavan, and T. Mitra, "Integrated scratchpad memory optimization and task scheduling for MPSoC architectures," in Proc. of CASES, 2006.
11. Hoesoek Yang and Soonhoi Ha, "Pipelined Data Parallel Task Mapping/Scheduling Technique for MPSoC," in Proc. of Design Automation and Test in Europe, pp.69-74, April 2009.
12. M. C. W. Geilen, T. Basten, and S. Stuijk, "Minimizing buffer requirements of synchronous dataflow graphs with model-checking," in Proc. of DAC '05, pp. 819-824, 2005.
13. A. H. Ghamarian, M. C. W. Geilen, S. Stuijk, T. Basten, A. Moonen, M. Bekooij, B. D. Theelen, and M. R. Mousavi, "Throughput analysis of synchronous data flow graphs," in Proc. of ACSD '06 IEEE, pp. 25-34, 2006.
14. S. Stuijk, M. C. W. Geilen, and T. Basten, "Exploring tradeoffs in buffer requirements and throughput constraints for synchronous dataflow graphs," in DAC '06 Proc, pp.899-904, 2006.
15. Y. Yang, M. Geilen, T. Basten, S. Stuijk, and H. Corporaal, "Exploring Trade-offs between Performance and Resource Requirements for Synchronous Dataflow Graphs," in Estimedia '09 Proc. , IEEE, pp. 96-105, 2009.
16. D. J. Wang and Y. H. Hu, "Fully static multiprocessor array realizability criteria for real-time recurrent dsp applications," IEEE Trans. On Signal Processing, 42(5), May 1994.
17. K. K. Parhi, "Static rate-optimal scheduling of iterative dataflow program via optimum unfoliding," IEEE Trans. on Computers, 40(2), February 1991.
18. S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee. "Software Synthesis from Dataow Graphs," Kluwer Academic Publishers, 1996.
19. http://jgap.sourceforge.net