Partitioning and pipelining for performance-constrained hardware/software systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 4, 1999, Pages 419-432

  Bakshi, Smita ^a,b   Gajski, Daniel D ^a,c  

^a IEEE   (United States)

^b Synplicity Inc   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital design; High performance; Image processing partitioning; Performance tradeoffs; Pipelining; System level

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; CONSTRAINT THEORY; DIGITAL SIGNAL PROCESSING; PIPELINE PROCESSING SYSTEMS;

HARDWARE/SOFTWARE PARTITIONING ALGORITHMS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033281192     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.805749     Document Type: Article

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