Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 899-904

  Stuijk, Sander ^a   Geilen, Marc ^a   Basten, Twan ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Buffering; Optimization; Synchronous dataflow; Throughput

Indexed keywords

CONSTRAINT THEORY; DATA FLOW ANALYSIS; ENERGY UTILIZATION; MULTIMEDIA SYSTEMS; OPTIMIZATION; THROUGHPUT;

BUFFERING; SYNCHRONOUS DATAFLOW; THROUGHPUT CONSTRAINTS;

GRAPH THEORY;

EID: 34347362802     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147138     Document Type: Conference Paper

References (20)

1. M. ADÉ ET AL. Data minimisation for synchronous data flow graphs emulated on dsp-fpga targets. In DAC'97, Proc. (1997), ACM, p. 64-69.
2. K. ALTISEN ET AL. A methodology for the construction of scheduled systems. In Int. Symp. on Formal Techniques in Real-Time and Fault-Tolerant Systems, Proc. (2000), Springer-Verlag, p. 106-120.
3. T. AMNELL ET AL. Times: a tool for schedulability analysis and code generation of real-time systems. In FORMATS'03, number 2791 in LNCS (2004), Springer-Verlag, p. 60-72.
4. S. BHATTACHARYYA ET AL. Software Synthesis from Dataflow Graphs. Kluwer, 1996.
5. S. BHATTACHARYYA ET AL. Synthesis of embedded software from synchronous dataflow specifications. Journal on VLSI Signal Process. Syst. 21, 2 (1999), p. 151-166.
6. J. BUCK. Scheduling Dynamic Dataflow Graphs with Bounded Memory using the Token Flow Model. PhD thesis, University of California, Berkeley, CA, 1993.
7. M. GEILEN, T. BASTEN, AND S. STUIJK. Minimising buffer requirements of synchronous dataflow graphs with model-checking. In DAC'05, Proc. (2005), ACM, p. 819-824.
8. A. GHAMARIAN, M. GEILEN, S. STUIJK, T. BASTEN, A. MOONEN, M. BEKOOIJ, B. THEELEN, AND M. MOUSAVI. Throughput analysis of synchronous data flow graphs. In ACSD'06, Proc. (2006), IEEE.
9. R. GOVINDARAJAN ET AL. Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks. Journal of VLSI Signal Processing 31, 3 (2002), p. 207-229.
10. C.-T. HWANG ET AL. A formal approach to the scheduling problem in high-level synthesis. IEEE Trans. on Computer-Aided Design 10, 4 (1991), p. 464-475.
11. E. LEE AND D. MESSERSCHMITT. Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans. on Comp. 36, 1 (1987), p. 24-35.
12. P. MURTHY AND S. BHATTACHARYY. Shared memory implementations of synchronous dataflow specifications. In DATE'00, Proc. (March 2000), IEEE, p. 404-410.
13. Q. NING AND G. GAO. A novel framework of register allocation for software pipelining. In Symp. on Principles of Programming Languages, Proc. (1993), ACM, p. 29-42.
14. H. OH AND S. HA. Efficient code synthesis from extended dataflow graphs. In DAC'02, Proc. (2002), IEEE, p. 275-280.
15. P. POPLAVKO, T. BASTEN, M. BEKOOIJ, J. VAN MEERBERGEN, AND B. MESMAN. Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. In Compilers, Architecture and Synthesis for Embedded Systems, CASES'03, Proc. (2003), ACM, p. 63-72.
16. S. RITZ ET AL. Scheduling for optimum data memory compaction in block diagram oriented software synthesis. In Int. Conf. on Acoustics, Speech, and Signal Processing, Proc. (1995), IEEE, p. 2651-2654.
17. S. SHUKLA AND R. GUPTA. A model checking approach to evaluating system level dynamic power management policies for embedded systems. In High-Level Design Validation and Test, Proc. (2001), IEEE, p. 53-57.
18. S. SRIRAM AND S. BHATTACHARYYA. Embedded Multiprocessors Scheduling and Synchronization. Marcel Dekker, 2000.
19. S. STUIJK, M. GEILEN, AND T. BASTEN. Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. Tech. Report, TU Eindhoven. http://www.es.ele.tue.nl/ esreports/esr-2006-01.pdf
20. 3: SDF for free. In ACSD'06, Proc. (2006), IEEE. http://www.es.ele.tue.nl/sdf3