-
1
-
-
85053146503
-
-
Synopsys Inc, USA COSSAP Usres Manual : VHDL Code generation
-
Synopsys Inc, 700 E Middlefield Rd Mountain View CA 94043. USA COSSAP Usres Manual : VHDL Code generation.
-
700 E Middlefield Rd Mountain View CA 94043
-
-
-
2
-
-
85053119118
-
Synthesis of parallel hardware implementions from synchronouns dataflow graph specification
-
Pacific Grove, Calfornisa, USA. November
-
MC Williamson and EA Lee. Synthesis of parallel hardware implementions from synchronouns dataflow graph specification, In 30th Asilomar Conference on Signals, System, and Computers, Pacific Grove, Calfornisa, USA. November 1996.
-
(1996)
30th Asilomar Conference on Signals, System, and Computers
-
-
Williamson, M.C.1
Lee, E.A.2
-
4
-
-
0029226904
-
High-level algorithm and architecture transformations for dsp synthesis
-
K. K. Parhi. High-level algorithm and architecture transformations for dsp synthesis. Journal of VLSI Signal Processing, 9:pp 121-143, 1995.
-
(1995)
Journal of VLSI Signal Processing
, vol.9
, pp. 121-143
-
-
Parhi, K.K.1
-
5
-
-
0000596527
-
Scheduling parallel computations
-
October
-
R. Reiter. Scheduling parallel computations. Journal of ACM, 15(4):pp. 590-599, October 1968.
-
(1968)
Journal of ACM
, vol.15
, Issue.4
, pp. 590-599
-
-
Reiter, R.1
-
6
-
-
0026108176
-
Static rate-optimal scheduling of iterative data-flow program via optimum unfoliding
-
February
-
K. K. Parhi. Static rate-optimal scheduling of iterative data-flow program via optimum unfoliding. IEEE Trans, on Computers, 40(2), February 1991.
-
(1991)
IEEE Trans, on Computers
, vol.40
, Issue.2
-
-
Parhi, K.K.1
-
7
-
-
0028396022
-
Rate-optimal dsp synthesis by pipeline and minimum unfolding
-
March
-
L. G. Jeng and L. G. Chen. Rate-optimal dsp synthesis by pipeline and minimum unfolding. IEEE Trans, on VLSI Systems, 2(1), March 1994.
-
(1994)
IEEE Trans, on VLSI Systems
, vol.2
, Issue.1
-
-
Jeng, L.G.1
Chen, L.G.2
-
8
-
-
0028428049
-
Fully static multiprocessor array readability criteria for real-time recurrent dsp applications
-
May
-
D. J. Wang and Y. H. Hu. Fully static multiprocessor array readability criteria for real-time recurrent dsp applications. IEEE Trans, on Signal Processing, 42(5), May 1994.
-
(1994)
IEEE Trans, on Signal Processing
, vol.42
, Issue.5
-
-
Wang, D.J.1
Hu, Y.H.2
-
9
-
-
0026384361
-
A globally static rate optimal scheduling from recursive dsp algorithms
-
May
-
L. G. Jeng and L. G. Chen. A globally static rate optimal scheduling from recursive dsp algorithms. In Proc. ICASSP, pp. 1005-1008, May 1991.
-
(1991)
Proc. ICASSP
, pp. 1005-1008
-
-
Jeng, L.G.1
Chen, L.G.2
-
10
-
-
84971459762
-
Unfolding and retiming data-flow dsp programs for rise multiprocessor scheduling
-
L. F. Chao and E. H. M. Sha. Unfolding and retiming data-flow dsp programs for rise multiprocessor scheduling. In Proc. ICASSP, volume 5, pp. 565-568, 1992.
-
(1992)
Proc. ICASSP
, vol.5
, pp. 565-568
-
-
Chao, L.F.1
Sha, E.H.M.2
-
11
-
-
0029267885
-
High-level dsp synthesis using concurrent transformations, scheduling and allocation
-
March
-
C. Y. Wang and K. K. Parhi. High-level dsp synthesis using concurrent transformations, scheduling and allocation. IEEE Trans, on CAD of IC and System, 14(3), March 1995.
-
(1995)
IEEE Trans, on CAD of IC and System
, vol.14
, Issue.3
-
-
Wang, C.Y.1
Parhi, K.K.2
-
12
-
-
0027629019
-
Data-flow transformations for critical path time reduction in high-level dsp synthesis
-
July
-
L. E. Lucke and K. K. Parhi. Data-flow transformations for critical path time reduction in high-level dsp synthesis. IEEE Trans, on CAD of IC and Systems, 12(7), July 1993.
-
(1993)
IEEE Trans, on CAD of IC and Systems
, vol.12
, Issue.7
-
-
Lucke, L.E.1
Parhi, K.K.2
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