ALD on high mobility channels: Engineering the proper gate stack passivation

ECS Transactions

Volumn 33, Issue 2, 2010, Pages 9-23

  Sioncke, S ^a   Lin, H C ^a   Adelmann, C ^a   Brammertz, G ^a   Delabie, A ^a   Conard, T ^a   Franquet, A ^a   Caymax, M ^a   Meuris, M ^a   Struyf, H ^a   De Gendt, S ^a   Heyns, M ^a   Fleischmann, C ^b   Temst, K ^b   Vantomme, A ^b   Muller M ^c   Kolbe, M ^c   Beckhoff, B ^c   Schmeisser, D ^d   Tallarida, M ^d  

^a IMEC   (Belgium)

^b KU LEUVEN   (Belgium)

^c PHYSIKALISCH TECHNISCHE BUNDESANSTALT   (Germany)

^d BRANDENBURG UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITION; GALLIUM ARSENIDE; III-V SEMICONDUCTORS; LOGIC GATES; SURFACE TREATMENT;

BULK PROPERTIES; FUTURE TECHNOLOGIES; GATE STACKS; HIGH MOBILITY CHANNELS; SURFACE OXIDE;

PASSIVATION;

EID: 79952568079     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3485237     Document Type: Conference Paper

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